14.3 Embedded Characteristics

  • In-order Pipeline with Dynamic Branch Prediction
  • ARM, Thumb-2, and Thumb-2EE Instruction Set Support
  • TrustZone Security Extensions
  • Harvard Level 1 Memory System with a Memory Management Unit (MMU)
  • 32 Kbytes Data Cache
  • 32 Kbytes Instruction Cache
  • 64-bit CPU System Bus Host Interface
  • ARM v7 Debug Architecture
  • Trace Support through an Embedded Trace Macrocell (ETM) Interface
  • Media Processing Engine (MPE) with NEON Technology
  • Jazelle Hardware Acceleration