30.7.2 PTC Interrupt Status Register
| Name: | PTC_ISR |
| Offset: | 0x30 |
| Reset: | 0x00 |
| Property: | Read/Write |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| IRQ3 | IRQ2 | IRQ1 | IRQ0 | NOTIFY0 | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bits 4, 5, 6, 7 – IRQx Interrupt to the Host
Used for communications between the host processor and the pPP. The firmware can set an IRQ event in fields IRQ0 to IRQ3. Any of the pPP IRQ0 to IRQ3 fields automatically rises the PTC_IRQ signal.
Bit 0 – NOTIFY0 Notification to the Firmware
Used for communications between the host processor and the pPP. The firmware is notified when a command is used.