47.2.1 USART/UART Characteristics

  • 32-data Transmit and Receive FIFOs
  • Programmable Baud Rate Generator
  • Baud Rate can be Independent of the Processor/Peripheral Clock
  • Comparison Function on Received Character
  • 5-bit to 9-bit Full-duplex Synchronous or Asynchronous Serial Communications
    • 1, 1.5 or 2 stop bits in Asynchronous mode or 1 or 2 stop bits in Synchronous mode
    • Parity generation and error detection
    • Framing error detection, overrun error detection
    • Digital filter on receive line
    • MSB- or LSB-first
    • Optional break generation and detection
    • By 8 or by 16 oversampling receiver frequency
    • Optional hardware handshaking RTS-CTS
    • Receiver timeout and transmitter timeguard
    • Optional Multidrop mode with address generation and detection
  • RS485 with Driver Control Signal
  • ISO7816, T = 0 or T = 1 Protocols for Interfacing with Smart Cards
    • NACK handling, error counter with repetition and iteration limit
  • IrDA Modulation and Demodulation
    • Communication at up to 115.2 kbit/s
  • SPI Mode
    • Host or client
    • Serial clock programmable phase and polarity
    • SPI Serial Clock (SCK) frequency up to fperipheral clock/6
  • LIN Mode
    • Compliant with LIN 1.3 and LIN 2.0 specifications
    • Host or client
    • Processing of frames with up to 256 data bytes
    • Response data length can be configurable or defined automatically by the identifier
    • Self-synchronization in client node configuration
    • Automatic processing and verification of the “synch break” and the “synch field”
    • “Synch break” detection even when partially superimposed with a data byte
    • Automatic identifier parity calculation/sending and verification
    • Parity sending and verification can be disabled
    • Automatic checksum calculation/sending and verification
    • Checksum sending and verification can be disabled
    • Support both “classic” and “enhanced” checksum types
    • Full LIN error checking and reporting
    • Frame Slot mode: host allocates slots to the scheduled frames automatically
    • Generation of the wakeup signal
  • Test Modes
    • Remote Loopback, Local Loopback, Automatic Echo
  • Supports Connection of:
    • Two DMA Controller (DMAC) channels
    • Offers buffer transfer without processor intervention
  • Functional Safety: Protection, Monitors and Reports
    • Register Write protection
    • Reports any write-protected access