Isolates the DDR pads from the CPU domain (VDDCORE).
Must be set after enabling the Self-refresh mode on the DDR memory and before
powering down on VDDCORE.
To enable Self-refresh mode, refer to the MPDDRC Low-power register
(MPDDRC_LPR) in the section "Multi-port DDR-SDRAM Controller" and to "Backup Mode
with DDR in Self-refresh" in the section "Electrical Characteristics".
| Value | Description |
|---|
| 0 |
Reset value. DDR Backup mode disabled. The DDR pads are not
isolated from CPU domain. |
| 1 |
DDR Backup mode enabled. The DDR pads are isolated from CPU domain (IOs are in memory state). |
