7.4 Write Cycle Timing

The length of the self-timed write cycle (t_WR) is defined as the amount of time from the Stop condition, which begins the internal write cycle, to the Start condition of the first device address byte sent to the AT24C16C, to which it subsequently responds with an ACK. Figure 7-4 shows this measurement. During the internally self-timed write cycle, any attempts to read from or write to the memory array will not be processed.

Figure 7-4. Write Cycle Timing