15.6.2.6 Peripheral Clock Masking
It is possible to disable or enable the clock for a peripheral in the AHB or APBx clock domain by writing the corresponding bit in the Clock Mask register ((APBxMASK) for additional information, refer to the APBAMASK register) to zero or one. Refer to the table below for the default state of each of the peripheral clocks.
Peripheral Clock | Default State |
---|---|
CLK_PAC0_APB | Enabled |
CLK_PM_APB | Enabled |
CLK_SYSCTRL_APB | Enabled |
CLK_GCLK_APB | Enabled |
CLK_WDT_APB | Enabled |
CLK_RTC_APB | Enabled |
CLK_EIC_APB | Enabled |
CLK_PAC1_APB | Enabled |
CLK_DSU_APB | Enabled |
CLK_NVMCTRL_APB | Enabled |
CLK_PORT_APB | Enabled |
CLK_PAC2_APB | Disabled |
CLK_SERCOMx_APB | Disabled |
CLK_TCx_APB | Disabled |
CLK_ADC_APB | Enabled |
CLK_AC_APB | Disabled |
CLK_DAC_APB | Disabled |
CLK_PTC_APB | Disabled |
When the APB clock for a module is not provided its registers cannot be read or written. The module can be re-enabled later by writing the corresponding mask bit to one.
A module may be connected to several clock domains (for instance, AHB and APB), in which case it will have several mask bits.