These bits select the generic clock that will be
configured. The value of the ID bit group versus module instance is shown in the
table below.
A power reset will reset the CLKCTRL register for all IDs, including the RTC. If the WRTLOCK bit of the corresponding ID is zero and the ID is not the RTC, a user reset will reset the CLKCTRL register for this ID.
After a power reset, the reset value of the
CLKCTRL register versus module instance is as shown in the next table.
Table 14-3. Generic Clock Selection ID and
CLKCTRL value after Power ResetModule Instance | Reset Value after Power Reset |
---|
| CLKCTRL.GEN | CLKCTRL.CLKEN | CLKCTRL.WRTLOCK |
---|
RTC | 0x00 | 0x00 | 0x00 |
WDT | 0x02 | 0x01 if WDT Enable bit in NVM
User Row written to one
0x00 if WDT Enable bit in NVM
User Row written to zero | 0x01 if WDT Always-On bit in
NVM User Row written to one
0x00 if WDT Always-On bit in
NVM User Row written to zero |
Others | 0x00 | 0x00 | 0x00 |
After a user reset, the reset value of the
CLKCTRL register versus module instance is as shown in the table below.
Table 14-4. Generic Clock Selection ID and CLKCTRL Value after User ResetModule Instance | Reset Value after a User Reset |
---|
| CLKCTRL.GEN | CLCTRL.CLKEN | CLKCTRL.WRTLOCK |
---|
RTC | 0x00 if WRTLOCK=0 and
CLKEN=0
No change if WRTLOCK=1
or CLKEN=1 | 0x00 if WRTLOCK=0 and CLKEN=0
No change if WRTLOCK=1 or CLKEN=1 | No change |
WDT | 0x02 if WRTLOCK=0
No change if WRTLOCK=1 | If WRTLOCK=0
0x01 if WDT Enable bit in NVM User
Row written to one
0x00 if WDT Enable bit in NVM User
Row written to zero
If WRTLOCK=1 no change | No change |
Others | 0x00 if WRTLOCK=0
No change if WRTLOCK=1 | 0x00 if WRTLOCK=0
No change if WRTLOCK=1 | No change |
Value | Name | Description |
---|
0x00 | GCLK_DFLL48M_REF | DFLL48M Reference |
0x01 | GCLK_WDT | WDT |
0x02 | GCLK_RTC | RTC |
0x03 | GCLK_EIC | EIC |
0x04 | GCLK_EVSYS_CHANNEL_0 | EVSYS_CHANNEL_0 |
0x05 | GCLK_EVSYS_CHANNEL_1 | EVSYS_CHANNEL_1 |
0x06 | GCLK_EVSYS_CHANNEL_2 | EVSYS_CHANNEL_2 |
0x07 | GCLK_EVSYS_CHANNEL_3 | EVSYS_CHANNEL_3 |
0x08 | GCLK_EVSYS_CHANNEL_4 | EVSYS_CHANNEL_4 |
0x09 | GCLK_EVSYS_CHANNEL_5 | EVSYS_CHANNEL_5 |
0x0A | GCLK_EVSYS_CHANNEL_6 | EVSYS_CHANNEL_6 |
0x0B | GCLK_EVSYS_CHANNEL_7 | EVSYS_CHANNEL_7 |
0x0C | GCLK_SERCOMx_SLOW | SERCOMx_SLOW |
0x0D | GCLK_SERCOM0_CORE | SERCOM0_CORE |
0x0E | GCLK_SERCOM1_CORE | SERCOM1_CORE |
0x0F | GCLK_SERCOM2_CORE | SERCOM2_CORE |
0x10 | GCLK_SERCOM3_CORE | SERCOM3_CORE |
0x11 | GCLK_SERCOM4_CORE | SERCOM4_CORE |
0x12 | GCLK_SERCOM5_CORE | SERCOM5_CORE |
0x13 | GCLK_TC0, GCLK_TC1 | TC0, TC1 |
0x14 | GCLK_TC2, GCLK_TC3 | TC2, TC3 |
0x15 | GCLK_TC4, GCLK_TC5 | TC4, TC5 |
0x16 | GCLK_TC6, GCLK_TC7 | TC6, TC7 |
0x17 | GCLK_ADC | ADC |
0x18 | GCLK_AC_DIG | AC_DIG |
0x19 | GCLK_AC_ANA | AC_ANA |
0x1A | GCLK_DAC | DAC |
0x1B | GCLK_PTC | PTC |
0x1C-0x3F | - | Reserved |