25.8.6 Interrupt Enable Set

Name: INTENSET
Offset: 0x0D
Reset: 0x00
Property: PAC Write-Protection

This register allows the user to disable an interrupt without read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).

Bit 76543210 
      RXCTXCDRE 
Access R/WR/WR/W 
Reset 000 

Bit 2 – RXC Receive Complete Interrupt Enable

Writing '0' to this bit has no effect.

Writing '1' to this bit will set the Receive Complete Interrupt Enable bit, which enables the Receive Complete interrupt.

ValueDescription
0 Receive Complete interrupt is disabled.
1 Receive Complete interrupt is enabled.

Bit 1 – TXC Transmit Complete Interrupt Enable

Writing '0' to this bit has no effect.

Writing '1' to this bit will set the Transmit Complete Interrupt Enable bit, which enables the Transmit Complete interrupt.

ValueDescription
0 Transmit Complete interrupt is disabled.
1 Transmit Complete interrupt is enabled.

Bit 0 – DRE Data Register Empty Interrupt Enable

Writing '0' to this bit has no effect.

Writing '1' to this bit will set the Data Register Empty Interrupt Enable bit, which enables the Data Register Empty interrupt.

ValueDescription
0 Data Register Empty interrupt is disabled.
1 Data Register Empty interrupt is enabled.