22.8.6 Interrupt Enable Set

Name: INTENSET
Offset: 0x14
Reset: 0x00000000
Property: Write-Protected

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
 EVDn EVDn EVDn EVDn EVDn EVDn EVDn EVDn  
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 OVRnOVRnOVRnOVRnOVRnOVRnOVRnOVRn 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 15,14,13,12,11,10,9,8 – EVDn  Channel n Event Detection Interrupt Enable [n=7..0]

Writing a zero to this bit has no effect.

Writing a one to this bit will set the Event Detected Channel n Interrupt Enable bit, which enables the Event Detected Channel n interrupt.

ValueDescription
0 The Event Detected Channel n interrupt is disabled.
1 The Event Detected Channel n interrupt is enabled.

Bits 7,6,5,4,3,2,1,0 – OVRn Channel n Overrun Interrupt Enable [n=7..0]

Writing a zero to this bit has no effect.

Writing a one to this bit will set the Overrun Channel n Interrupt Enable bit, which enables the Overrun Channel n interrupt.

ValueDescription
0 The Overrun Channel n interrupt is disabled.
1 The Overrun Channel n interrupt is enabled.