26.10.5 Interrupt Enable Clear
Name: | INTENCLR |
Offset: | 0x0C |
Reset: | 0x00 |
Property: | PAC Write-Protection |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
SB | MB | ||||||||
Access | R/W | R/W | |||||||
Reset | 0 | 0 |
Bit 1 – SB Client on Bus Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Client on Bus Interrupt Enable bit, which disables the Client on Bus interrupt.
Value | Description |
---|---|
0 | The Client on Bus interrupt is disabled. |
1 | The Client on Bus interrupt is enabled. |
Bit 0 – MB Host on Bus Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Host on Bus Interrupt Enable bit, which disables the Host on Bus interrupt.
Value | Description |
---|---|
0 | The Host on Bus interrupt is disabled. |
1 | The Host on Bus interrupt is enabled. |