32.12.3 Digital Frequency Locked Loop (DFLL48M) Characteristics
Table below provides the characteristics of the DFLL48M.
| Symbol | Parameter | Conditions | Min. | Typ. | Max. | Units |
|---|---|---|---|---|---|---|
| fOUT | Average Output frequency | fREF = XOSC32K 32.768 kHz | 47 | 48 | 49 | MHz |
| fREF | Reference frequency | 0.732 | 32.768 | 35.1 | kHz | |
| Jitter | Period jitter | fREF = XOSC32K 32.768 kHz | - | - | 0.42 | ns |
| IDFLL | Power consumption on VDDIN | fREF = XOSC32K 32.768 kHz. For SAMD20 revision C devices | - | 397 | - | μA |
| fREF = XOSC32K 32.768 kHz. For SAMD20 revision D devices and later. | - | 292 | - | |||
| tLOCK | Lock time | fREF = XOSC32K 32.768 kHz DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512 DFLLCTRL.BPLCKC = 1 DFLLCTRL.QLDIS = 0 DFLLCTRL.CCDIS = 1 DFLLMUL.FSTEP = 10 | 100 | 200 | 500 | μs |
| Quick lock disabled, Chill cycle disabled, CSTEP = 3, FSTEP = 1, fREF = XOSC32K 32.768 kHz | - | 600 | - |
Note:
- Refer to the revision C/revision B errata related to the DFLL48M.
- All parts are tested in production to be able to use the DFLL as main CPU clock whether in DFLL Closed Loop mode with an external OSC reference or in DFLL Closed Loop mode using the internal OSC8M (Only applicable for revision C).