21.9.2 Data Direction Clear

This register allows the user to set one or more I/O pins as an input, without doing a read-modify-write operation. Changes in this register will also be reflected in the Data Direction (DIR), Data Direction Toggle (DIRTGL) and Data Direction Set (DIRSET) registers.

Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80.
Name: DIRCLR
Offset: 0x04
Reset: 0x00000000
Property: PAC Write-Protection

Bit 3130292827262524 
 DIRCLR[31:24] 
Access RWRWRWRWRWRWRWRW 
Reset 00000000 
Bit 2322212019181716 
 DIRCLR[23:16] 
Access RWRWRWRWRWRWRWRW 
Reset 00000000 
Bit 15141312111098 
 DIRCLR[15:8] 
Access RWRWRWRWRWRWRWRW 
Reset 00000000 
Bit 76543210 
 DIRCLR[7:0] 
Access RWRWRWRWRWRWRWRW 
Reset 00000000 

Bits 31:0 – DIRCLR[31:0] Port Data Direction Clear

Writing a '0' to a bit has no effect.

Writing a '1' to a bit will clear the corresponding bit in the DIR register, which configures the I/O pin as an input.
ValueDescription
0

The corresponding I/O pin in the PORT group will keep its configuration.

1 The corresponding I/O pin in the PORT group is configured as input.