Reset status register for reading the reset source from the application code
Clock control
Controls CPU, AHB and APB system
clocks
Multiple clock sources and division factor from GCLK
Clock prescaler with 1x to 128x division
Safe run-time clock switching from GCLK
Module-level clock gating through maskable peripheral clocks
Clock failure detector
Power management control
Sleep modes: IDLE, STANDBY
SleepWalking support on GCLK clocks
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
