28.6.13 Sleep Mode Operation

The run in the Standby bit in the Control A register (CTRLA.RUNSTDBY) controls the behavior of the ADC during Standby Sleep mode. When CTRLA.RUNSTDBY = 0, the ADC is disabled during sleep, but maintains its current configuration. When CTRLA.RUNSTDBY = 1, the ADC continues to operate during sleep. When CTRLA.RUNSTDBY = 0, the analog blocks are powered off for the lowest power consumption. This necessitates a start-up time delay when the system returns from sleep.

When CTRLA.RUNSTDBY = 1, any enabled ADC interrupt source can wake-up the CPU, except the OVERRUN interrupt.. While the CPU is sleeping, ADC conversion can only be triggered by events.