36.7.3 20-pin IDC JTAG Connector
For debuggers and/or programmers that support the 20-pin IDC JTAG Connector, e.g. the SAM-ICE, the signals should be connected as shown in the next figure with details described in the table.
| Header Signal Name | Description |
|---|---|
| SWDCLK | Serial wire clock pin |
| SWDIO | Serial wire bidirectional data pin |
| RESET | Target device reset pin, active low |
| VCC | Target voltage sense, should be connected to the device VDD |
| GND | Ground |
| GND* | These pins are reserved for firmware extension purposes. They can be left open or connected to GND in normal debug environment. They are not essential for SWD in general. |