2 Pin Diagrams

Figure 2-1. 8-Pin PDIP, SOIC, DFN

Figure 2-2. 14-Pin PDIP, SOIC, TSSOP

Figure 2-3. 16-Pin QFN

Note: It is recommended that the exposed bottom pad be connected to V_SS, however, it must not be the only V_SS connection to the device.