39 Register Summary
| Offset | Name | Bit Pos. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 | INDF0 | 7:0 | INDF0[7:0] | |||||||
| 0x01 | INDF1 | 7:0 | INDF1[7:0] | |||||||
| 0x02 | PCL | 7:0 | PCL[7:0] | |||||||
| 0x03 | STATUS | 7:0 | TO | PD | Z | DC | C | |||
| 0x04 | FSR0 | 7:0 | FSR0[7:0] | |||||||
| 15:8 | FSR0[15:8] | |||||||||
| 0x06 | FSR1 | 7:0 | FSR1[7:0] | |||||||
| 15:8 | FSR1[15:8] | |||||||||
| 0x08 | BSR | 7:0 | BSR[5:0] | |||||||
| 0x09 | WREG | 7:0 | WREG[7:0] | |||||||
| 0x0A | PCLATH | 7:0 | PCLATH[6:0] | |||||||
| 0x0B | INTCON | 7:0 | GIE | PEIE | INTEDG | |||||
| 0x0C | PORTA | 7:0 | RA5 | RA4 | RA3 | RA2 | RA1 | RA0 | ||
0x0D | Reserved | |||||||||
| 0x0E | PORTC | 7:0 | RC5 | RC4 | RC3 | RC2 | RC1 | RC0 | ||
0x0F ... 0x11 | Reserved | |||||||||
| 0x12 | TRISA | 7:0 | TRISA5 | TRISA4 | Reserved | TRISA2 | TRISA1 | TRISA0 | ||
0x13 | Reserved | |||||||||
| 0x14 | TRISC | 7:0 | TRISC5 | TRISC4 | TRISC3 | TRISC2 | TRISC1 | TRISC0 | ||
0x15 ... 0x17 | Reserved | |||||||||
| 0x18 | LATA | 7:0 | LATA5 | LATA4 | LATA2 | LATA1 | LATA0 | |||
0x19 | Reserved | |||||||||
| 0x1A | LATC | 7:0 | LATC5 | LATC4 | LATC3 | LATC2 | LATC1 | LATC0 | ||
0x1B ... 0x8B | Reserved | |||||||||
| 0x8C | PIR0 | 7:0 | TMR0IF | IOCIF | INTF | |||||
| 0x8D | PIR1 | 7:0 | TMR2IF | TMR3GIF | TMR3IF | TMR1GIF | TMR1IF | ACTIF | NVMIF | |
| 0x8E | PIR2 | 7:0 | CLC2IF | CLC1IF | NCO1IF | CCP2IF | CCP1IF | TMR6IF | TMR4IF | |
| 0x8F | PIR3 | 7:0 | BCL1IF | SSP1IF | RC1IF | TX1IF | CLC4IF | CLC3IF | ||
| 0x90 | PIR4 | 7:0 | ZCDIF | ADTIF | ADIF | CM1IF | ||||
0x91 ... 0x95 | Reserved | |||||||||
| 0x96 | PIE0 | 7:0 | TMR0IE | IOCIE | INTE | |||||
| 0x97 | PIE1 | 7:0 | TMR2IE | TMR3GIE | TMR3IE | TMR1GIE | TMR1IE | ACTIE | NVMIE | |
| 0x98 | PIE2 | 7:0 | CLC2IE | CLC1IE | NCO1IE | CCP2IE | CCP1IE | TMR6IE | TMR4IE | |
| 0x99 | PIE3 | 7:0 | BCL1IE | SSP1IE | RC1IE | TX1IE | CLC4IE | CLC3IE | ||
| 0x9A | PIE4 | 7:0 | ZCDIE | ADTIE | ADIE | CM1IE | ||||
0x9B ... 0x018B | Reserved | |||||||||
| 0x018C | WDTCON | 7:0 | CS | PS[4:0] | SEN | |||||
| 0x018D | BORCON | 7:0 | SBOREN | BORRDY | ||||||
| 0x018E | PCON0 | 7:0 | STKOVF | STKUNF | RWDT | RMCLR | RI | POR | BOR | |
| 0x018F | PCON1 | 7:0 | MEMV | |||||||
0x0190 ... 0x019B | Reserved | |||||||||
| 0x019C | TMR0L | 7:0 | TMR0L[7:0] | |||||||
| 0x019D | TMR0H | 7:0 | TMR0H[7:0] | |||||||
| 0x019E | T0CON0 | 7:0 | EN | OUT | MD16 | OUTPS[3:0] | ||||
| 0x019F | T0CON1 | 7:0 | CS[2:0] | ASYNC | CKPS[3:0] | |||||
0x01A0 ... 0x020D | Reserved | |||||||||
| 0x020E | OSCCON2 | 7:0 | COSC[2:0] | |||||||
| 0x020F | OSCCON3 | 7:0 | SOSCPWR | |||||||
| 0x0210 | OSCSTAT | 7:0 | HFOR | MFOR | LFOR | SOR | ADOR | SFOR | ||
| 0x0211 | OSCEN | 7:0 | HFOEN | MFOEN | LFOEN | SOSCEN | ADOEN | |||
| 0x0212 | OSCTUNE | 7:0 | TUN[5:0] | |||||||
| 0x0213 | OSCFRQ | 7:0 | FRQ[2:0] | |||||||
| 0x0214 | ACTCON | 7:0 | ACTEN | ACTUD | ACTLOCK | ACTORS | ||||
0x0215 ... 0x028B | Reserved | |||||||||
| 0x028C | TMR1 | 7:0 | TMR1[7:0] | |||||||
| 15:8 | TMR1[15:8] | |||||||||
| 0x028E | T1CON | 7:0 | CKPS[1:0] | SYNC | RD16 | ON | ||||
| 0x028F | T1GCON | 7:0 | GE | GPOL | GTM | GSPM | GGO/DONE | GVAL | ||
| 0x0290 | T1GATE | 7:0 | GSS[4:0] | |||||||
| 0x0291 | T1CLK | 7:0 | CS[4:0] | |||||||
| 0x0292 | TMR3 | 7:0 | TMR3[7:0] | |||||||
| 15:8 | TMR3[15:8] | |||||||||
| 0x0294 | T3CON | 7:0 | CKPS[1:0] | SYNC | RD16 | ON | ||||
| 0x0295 | T3GCON | 7:0 | GE | GPOL | GTM | GSPM | GGO/DONE | GVAL | ||
| 0x0296 | T3GATE | 7:0 | GSS[4:0] | |||||||
| 0x0297 | T3CLK | 7:0 | CS[4:0] | |||||||
0x0298 ... 0x030B | Reserved | |||||||||
| 0x030C | T2TMR | 7:0 | T2TMR[7:0] | |||||||
| 0x030D | T2PR | 7:0 | T2PR[7:0] | |||||||
| 0x030E | T2CON | 7:0 | ON | CKPS[2:0] | OUTPS[3:0] | |||||
| 0x030F | T2HLT | 7:0 | PSYNC | CPOL | CSYNC | MODE[4:0] | ||||
| 0x0310 | T2CLKCON | 7:0 | CS[3:0] | |||||||
| 0x0311 | T2RST | 7:0 | RSEL[3:0] | |||||||
| 0x0312 | T4TMR | 7:0 | T4TMR[7:0] | |||||||
| 0x0313 | T4PR | 7:0 | T4PR[7:0] | |||||||
| 0x0314 | T4CON | 7:0 | ON | CKPS[2:0] | OUTPS[3:0] | |||||
| 0x0315 | T4HLT | 7:0 | PSYNC | CPOL | CSYNC | MODE[4:0] | ||||
| 0x0316 | T4CLKCON | 7:0 | CS[3:0] | |||||||
| 0x0317 | T4RST | 7:0 | RSEL[3:0] | |||||||
| 0x0318 | T6TMR | 7:0 | T6TMR[7:0] | |||||||
| 0x0319 | T6PR | 7:0 | T6PR[7:0] | |||||||
| 0x031A | T6CON | 7:0 | ON | CKPS[2:0] | OUTPS[3:0] | |||||
| 0x031B | T6HLT | 7:0 | PSYNC | CPOL | CSYNC | MODE[4:0] | ||||
| 0x031C | T6CLKCON | 7:0 | CS[3:0] | |||||||
| 0x031D | T6RST | 7:0 | RSEL[3:0] | |||||||
0x031E ... 0x038B | Reserved | |||||||||
| 0x038C | CCPR1 | 7:0 | CCPR[7:0] | |||||||
| 15:8 | CCPR[15:8] | |||||||||
| 0x038E | CCP1CON | 7:0 | EN | OUT | FMT | MODE[3:0] | ||||
| 0x038F | CCP1CAP | 7:0 | CTS[3:0] | |||||||
| 0x0390 | CCPR2 | 7:0 | CCPR[7:0] | |||||||
| 15:8 | CCPR[15:8] | |||||||||
| 0x0392 | CCP2CON | 7:0 | EN | OUT | FMT | MODE[3:0] | ||||
| 0x0393 | CCP2CAP | 7:0 | CTS[3:0] | |||||||
0x0394 ... 0x039E | Reserved | |||||||||
| 0x039F | CCPTMRS0 | 7:0 | C2TSEL[1:0] | C1TSEL[1:0] | ||||||
0x03A0 ... 0x040B | Reserved | |||||||||
| 0x040C | PWM3DC | 7:0 | DCL[1:0] | |||||||
| 15:8 | DCH[7:0] | |||||||||
| 0x040E | PWM3CON | 7:0 | EN | OUT | POL | |||||
| 0x040F | PWM4DC | 7:0 | DCL[1:0] | |||||||
| 15:8 | DCH[7:0] | |||||||||
| 0x0411 | PWM4CON | 7:0 | EN | OUT | POL | |||||
| 0x0412 | PWM5DC | 7:0 | DCL[1:0] | |||||||
| 15:8 | DCH[7:0] | |||||||||
| 0x0414 | PWM5CON | 7:0 | EN | OUT | POL | |||||
0x0415 ... 0x041E | Reserved | |||||||||
| 0x041F | PWMTMRS0 | 7:0 | P5TSEL[1:0] | P4TSEL[1:0] | P3TSEL[1:0] | |||||
0x0420 ... 0x048B | Reserved | |||||||||
| 0x048C | NCO1ACC | 7:0 | ACC[7:0] | |||||||
| 15:8 | ACC[15:8] | |||||||||
| 23:16 | ACC[19:16] | |||||||||
| 0x048F | NCO1INC | 7:0 | INC[7:0] | |||||||
| 15:8 | INC[15:8] | |||||||||
| 23:16 | INC[19:16] | |||||||||
| 0x0492 | NCO1CON | 7:0 | EN | OUT | POL | PFM | ||||
| 0x0493 | NCO1CLK | 7:0 | PWS[2:0] | CKS[3:0] | ||||||
0x0494 ... 0x058B | Reserved | |||||||||
| 0x058C | CLCnCON | 7:0 | EN | OUT | INTP | INTN | MODE[2:0] | |||
| 0x058D | CLCnPOL | 7:0 | POL | G4POL | G3POL | G2POL | G1POL | |||
| 0x058E | CLCnSEL0 | 7:0 | D1S[5:0] | |||||||
| 0x058F | CLCnSEL1 | 7:0 | D2S[5:0] | |||||||
| 0x0590 | CLCnSEL2 | 7:0 | D3S[5:0] | |||||||
| 0x0591 | CLCnSEL3 | 7:0 | D4S[5:0] | |||||||
| 0x0592 | CLCnGLS0 | 7:0 | G1D4T | G1D4N | G1D3T | G1D3N | G1D2T | G1D2N | G1D1T | G1D1N |
| 0x0593 | CLCnGLS1 | 7:0 | G2D4T | G2D4N | G2D3T | G2D3N | G2D2T | G2D2N | G2D1T | G2D1N |
| 0x0594 | CLCnGLS2 | 7:0 | G3D4T | G3D4N | G3D3T | G3D3N | G3D2T | G3D2N | G3D1T | G3D1N |
| 0x0595 | CLCnGLS3 | 7:0 | G4D4T | G4D4N | G4D3T | G4D3N | G4D2T | G4D2N | G4D1T | G4D1N |
| 0x0596 | CLCSELECT | 7:0 | SLCT[2:0] | |||||||
| 0x0597 | CLCDATA | 7:0 | CLC4OUT | CLC3OUT | CLC2OUT | CLC1OUT | ||||
0x0598 ... 0x060B | Reserved | |||||||||
| 0x060C | RC1REG | 7:0 | RCREG[7:0] | |||||||
| 0x060D | TX1REG | 7:0 | TXREG[7:0] | |||||||
| 0x060E | SP1BRG | 7:0 | SPBRG[7:0] | |||||||
| 15:8 | SPBRG[15:8] | |||||||||
| 0x0610 | RC1STA | 7:0 | SPEN | RX9 | SREN | CREN | ADDEN | FERR | OERR | RX9D |
| 0x0611 | TX1STA | 7:0 | CSRC | TX9 | TXEN | SYNC | SENDB | BRGH | TRMT | TX9D |
| 0x0612 | BAUD1CON | 7:0 | ABDOVF | RCIDL | SCKP | BRG16 | WUE | ABDEN | ||
0x0613 ... 0x068B | Reserved | |||||||||
| 0x068C | SSP1BUF | 7:0 | BUF[7:0] | |||||||
| 0x068D | SSP1ADD | 7:0 | ADD[7:0] | |||||||
| 0x068E | SSP1MSK | 7:0 | MSK[6:0] | MSK0 | ||||||
| 0x068F | SSP1STAT | 7:0 | SMP | CKE | D/A | P | S | R/W | UA | BF |
| 0x0690 | SSP1CON1 | 7:0 | WCOL | SSPOV | SSPEN | CKP | SSPM[3:0] | |||
| 0x0691 | SSP1CON2 | 7:0 | GCEN | ACKSTAT | ACKDT | ACKEN | RCEN | PEN | RSEN | SEN |
| 0x0692 | SSP1CON3 | 7:0 | ACKTIM | PCIE | SCIE | BOEN | SDAHT | SBCDE | AHEN | DHEN |
0x0693 ... 0x100B | Reserved | |||||||||
| 0x100C | FVRCON | 7:0 | EN | RDY | TSEN | TSRNG | CDAFVR[1:0] | ADFVR[1:0] | ||
| 0x100D | CPCON | 7:0 | CPON[1:0] | CPOS | CPREQ | CPT | CPRDY | |||
0x100E ... 0x101E | Reserved | |||||||||
| 0x101F | ZCDCON | 7:0 | SEN | OUT | POL | INTP | INTN | |||
0x1020 ... 0x108B | Reserved | |||||||||
| 0x108C | CM1CON0 | 7:0 | EN | OUT | POL | SP | HYS | SYNC | ||
| 0x108D | CM1CON1 | 7:0 | INTP | INTN | ||||||
| 0x108E | CM1NCH | 7:0 | NCH[2:0] | |||||||
| 0x108F | CM1PCH | 7:0 | PCH[2:0] | |||||||
0x1090 ... 0x109E | Reserved | |||||||||
| 0x109F | CMOUT | 7:0 | C1OUT | |||||||
0x10A0 ... 0x110B | Reserved | |||||||||
| 0x110C | DAC1CON | 7:0 | EN | REFRNG | OE[1:0] | PSS[1:0] | NSS | |||
| 0x110D | DAC1DATL | 7:0 | DAC1R[7:0] | |||||||
0x110E ... 0x1C8B | Reserved | |||||||||
| 0x1C8C | NVMADR | 7:0 | NVMADR[7:0] | |||||||
| 15:8 | NVMADR[14:8] | |||||||||
| 0x1C8E | NVMDAT | 7:0 | NVMDAT[7:0] | |||||||
| 15:8 | NVMDAT[13:8] | |||||||||
| 0x1C90 | NVMCON1 | 7:0 | NVMREGS | LWLO | FREE | WRERR | WREN | WR | RD | |
| 0x1C91 | NVMCON2 | 7:0 | NVMCON2[7:0] | |||||||
0x1C92 ... 0x1D0B | Reserved | |||||||||
| 0x1D0C | ADLTH | 7:0 | LTH[7:0] | |||||||
| 15:8 | LTH[15:8] | |||||||||
| 0x1D0E | ADUTH | 7:0 | UTH[7:0] | |||||||
| 15:8 | UTH[15:8] | |||||||||
| 0x1D10 | ADERR | 7:0 | ERR[7:0] | |||||||
| 15:8 | ERR[15:8] | |||||||||
| 0x1D12 | ADSTPT | 7:0 | STPT[7:0] | |||||||
| 15:8 | STPT[15:8] | |||||||||
| 0x1D14 | ADFLTR | 7:0 | FLTR[7:0] | |||||||
| 15:8 | FLTR[15:8] | |||||||||
| 0x1D16 | ADACC | 7:0 | ACC[7:0] | |||||||
| 15:8 | ACC[15:8] | |||||||||
| 23:16 | ACC[17:16] | |||||||||
| 0x1D19 | ADCNT | 7:0 | CNT[7:0] | |||||||
| 0x1D1A | ADRPT | 7:0 | RPT[7:0] | |||||||
| 0x1D1B | ADPREV | 7:0 | PREV[7:0] | |||||||
| 15:8 | PREV[15:8] | |||||||||
| 0x1D1D | ADRES | 7:0 | RES[7:0] | |||||||
| 15:8 | RES[15:8] | |||||||||
| 0x1D1F | ADPCH | 7:0 | PCH[5:0] | |||||||
0x1D20 | Reserved | |||||||||
| 0x1D21 | ADACQ | 7:0 | ACQ[7:0] | |||||||
| 15:8 | ACQ[12:8] | |||||||||
| 0x1D23 | ADCAP | 7:0 | CAP[4:0] | |||||||
| 0x1D24 | ADPRE | 7:0 | PRE[7:0] | |||||||
| 15:8 | PRE[12:8] | |||||||||
| 0x1D26 | ADCON0 | 7:0 | ON | CONT | CS | FM | GO | |||
| 0x1D27 | ADCON1 | 7:0 | PPOL | IPEN | GPOL | PCSC | DSEN | |||
| 0x1D28 | ADCON2 | 7:0 | PSIS | CRS[2:0] | ACLR | MD[2:0] | ||||
| 0x1D29 | ADCON3 | 7:0 | CALC[2:0] | SOI | TMD[2:0] | |||||
| 0x1D2A | ADSTAT | 7:0 | AOV | UTHR | LTHR | MATH | STAT[2:0] | |||
| 0x1D2B | ADREF | 7:0 | PREF[1:0] | |||||||
| 0x1D2C | ADACT | 7:0 | ACT[5:0] | |||||||
| 0x1D2D | ADCLK | 7:0 | CS[5:0] | |||||||
| 0x1D2E | ADCG1A | 7:0 | CGA5 | CGA4 | CGA2 | CGA1 | CGA0 | |||
0x1D2F | Reserved | |||||||||
| 0x1D30 | ADCG1C | 7:0 | CGC5 | CGC4 | CGC3 | CGC2 | CGC1 | CGC0 | ||
0x1D31 ... 0x1D8B | Reserved | |||||||||
| 0x1D8C | RA0PPS | 7:0 | RA0PPS[5:0] | |||||||
| 0x1D8D | RA1PPS | 7:0 | RA1PPS[5:0] | |||||||
| 0x1D8E | RA2PPS | 7:0 | RA2PPS[5:0] | |||||||
0x1D8F | Reserved | |||||||||
| 0x1D90 | RA4PPS | 7:0 | RA4PPS[5:0] | |||||||
| 0x1D91 | RA5PPS | 7:0 | RA5PPS[5:0] | |||||||
0x1D92 ... 0x1D9B | Reserved | |||||||||
| 0x1D9C | RC0PPS | 7:0 | RC0PPS[5:0] | |||||||
| 0x1D9D | RC1PPS | 7:0 | RC1PPS[5:0] | |||||||
| 0x1D9E | RC2PPS | 7:0 | RC2PPS[5:0] | |||||||
| 0x1D9F | RC3PPS | 7:0 | RC3PPS[5:0] | |||||||
| 0x1DA0 | RC4PPS | 7:0 | RC4PPS[5:0] | |||||||
| 0x1DA1 | RC5PPS | 7:0 | RC5PPS[5:0] | |||||||
0x1DA2 ... 0x1E0B | Reserved | |||||||||
| 0x1E0C | PPSLOCK | 7:0 | PPSLOCKED | |||||||
| 0x1E0D | INTPPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1E0E | T0CKIPPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1E0F | T1CKIPPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1E10 | T1GPPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1E11 | T3CKIPPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1E12 | T3GPPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
0x1E13 ... 0x1E18 | Reserved | |||||||||
| 0x1E19 | T2INPPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1E1A | T4INPPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1E1B | T6INPPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
0x1E1C ... 0x1E1D | Reserved | |||||||||
| 0x1E1E | CCP1PPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1E1F | CCP2PPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
0x1E20 ... 0x1E3C | Reserved | |||||||||
| 0x1E3D | CLCIN0PPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1E3E | CLCIN1PPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1E3F | CLCIN2PPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1E40 | CLCIN3PPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1E41 | RX1PPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1E42 | CK1PPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
0x1E43 ... 0x1E46 | Reserved | |||||||||
| 0x1E47 | SSP1CLKPPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1E48 | SSP1DATPPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1E49 | SSP1SSPPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
0x1E4A ... 0x1E4F | Reserved | |||||||||
| 0x1E50 | ADACTPPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
0x1E51 ... 0x1E8B | Reserved | |||||||||
| 0x1E8C | ANSELA | 7:0 | ANSELA5 | ANSELA4 | ANSELA2 | ANSELA1 | ANSELA0 | |||
| 0x1E8D | WPUA | 7:0 | WPUA5 | WPUA4 | WPUA3 | WPUA2 | WPUA1 | WPUA0 | ||
| 0x1E8E | ODCONA | 7:0 | ODCA5 | ODCA4 | ODCA2 | ODCA1 | ODCA0 | |||
| 0x1E8F | SLRCONA | 7:0 | SLRA5 | SLRA4 | SLRA2 | SLRA1 | SLRA0 | |||
| 0x1E90 | INLVLA | 7:0 | INLVLA5 | INLVLA4 | INLVLA3 | INLVLA2 | INLVLA1 | INLVLA0 | ||
| 0x1E91 | IOCAP | 7:0 | IOCAP5 | IOCAP4 | IOCAP3 | IOCAP2 | IOCAP1 | IOCAP0 | ||
| 0x1E92 | IOCAN | 7:0 | IOCAN5 | IOCAN4 | IOCAN3 | IOCAN2 | IOCAN1 | IOCAN0 | ||
| 0x1E93 | IOCAF | 7:0 | IOCAF5 | IOCAF4 | IOCAF3 | IOCAF2 | IOCAF1 | IOCAF0 | ||
0x1E94 ... 0x1E9F | Reserved | |||||||||
| 0x1EA0 | ANSELC | 7:0 | ANSELC5 | ANSELC4 | ANSELC3 | ANSELC2 | ANSELC1 | ANSELC0 | ||
| 0x1EA1 | WPUC | 7:0 | WPUC5 | WPUC4 | WPUC3 | WPUC2 | WPUC1 | WPUC0 | ||
| 0x1EA2 | ODCONC | 7:0 | ODCC5 | ODCC4 | ODCC3 | ODCC2 | ODCC1 | ODCC0 | ||
| 0x1EA3 | SLRCONC | 7:0 | SLRC5 | SLRC4 | SLRC3 | SLRC2 | SLRC1 | SLRC0 | ||
| 0x1EA4 | INLVLC | 7:0 | INLVLC5 | INLVLC4 | INLVLC3 | INLVLC2 | INLVLC1 | INLVLC0 | ||
| 0x1EA5 | IOCCP | 7:0 | IOCCP5 | IOCCP4 | IOCCP3 | IOCCP2 | IOCCP1 | IOCCP0 | ||
| 0x1EA6 | IOCCN | 7:0 | IOCCN5 | IOCCN4 | IOCCN3 | IOCCN2 | IOCCN1 | IOCCN0 | ||
| 0x1EA7 | IOCCF | 7:0 | IOCCF5 | IOCCF4 | IOCCF3 | IOCCF2 | IOCCF1 | IOCCF0 | ||
0x1EA8 ... 0x1EE0 | Reserved | |||||||||
| 0x1EE1 | RA1I2C | 7:0 | SLEW | PU[1:0] | TH[1:0] | |||||
| 0x1EE2 | RA2I2C | 7:0 | SLEW | PU[1:0] | TH[1:0] | |||||
0x1EE3 ... 0x1EE8 | Reserved | |||||||||
| 0x1EE9 | RC0I2C | 7:0 | SLEW | PU[1:0] | TH[1:0] | |||||
| 0x1EEA | RC1I2C | 7:0 | SLEW | PU[1:0] | TH[1:0] | |||||
0x1EEB ... 0x8004 | Reserved | |||||||||
| 0x8005 | REVISIONID | 7:0 | MJRREV[1:0] | MNRREV[5:0] | ||||||
| 15:8 | Reserved | Reserved | MJRREV[5:2] | |||||||
| 0x8006 | DEVICEID | 7:0 | DEV[7:0] | |||||||
| 15:8 | Reserved | Reserved | DEV[11:8] | |||||||
| 0x8007 | CONFIG1 | 7:0 | RSTOSC[2:0] | FEXTOSC[1:0] | ||||||
| 15:8 | VDDAR | CLKOUTEN | ||||||||
| 0x8008 | CONFIG2 | 7:0 | BOREN[1:0] | WDTE[1:0] | PWRTS[1:0] | MCLRE | ||||
| 15:8 | DEBUG | STVREN | PPS1WAY | ZCD | BORV | DACAUTOEN | ||||
| 0x8009 | CONFIG3 | 7:0 | ||||||||
| 15:8 | ||||||||||
| 0x800A | CONFIG4 | 7:0 | WRTAPP | SAFEN | BBEN | BBSIZE[2:0] | ||||
| 15:8 | LVP | WRTSAF | WRTD | WRTC | WRTB | |||||
| 0x800B | CONFIG5 | 7:0 | CPD | CP | ||||||
| 15:8 | ||||||||||