3 Pin Allocation Tables

Table 3-1. 8-Pin Allocation Table
I/O	8-Pin PDIP SOIC DFN	ADC	DAC	Comparator	ZCD	Timers	CCP/PWM	CLC	MSSP	EUSART	IOC	Interrupt	Basic
RA0	7	ANA0	DAC1OUT1	C1IN0+	—	T3CKI⁽¹⁾ T3G⁽¹⁾ T4IN⁽¹⁾	—	CLCIN3⁽¹⁾	—	CK1^(1,3)	IOCA0	—	ICSPDAT ICDDAT
RA1	6	ANA1 V_REF+ (ADC)	DAC1REF0+	C1IN0-	—	T6IN⁽¹⁾	—	CLCIN2⁽¹⁾	SCL1^(1,3) SCK1^(1,3)	RX1⁽¹⁾ DT1^(1,3)	IOCA1	—	ICSPCLK ICDCLK
RA2	5	ANA2	DAC1REF0-	—	ZCD1	T0CKI⁽¹⁾	—	—	SDA1^(1,3) SDI1^(1,3)	—	IOCA2	INT⁽¹⁾	—
RA3	4	—	—	—	—	—	—	CLCIN0 ⁽¹⁾	SS1⁽¹⁾	—	IOCA3	—	MCLR V_PP
RA4	3	ANA4	—	C1IN1-	—	T1G⁽¹⁾	—	—	—	—	IOCA4	—	CLKOUT SOSCO
RA5	2	ANA5 ADACT⁽¹⁾	—	—	—	T1CKI⁽¹⁾ T2IN⁽¹⁾	CCP1⁽¹⁾ CCP2⁽¹⁾	CLCIN1⁽¹⁾	—	—	IOCA5	—	CLKIN SOSCI
V_DD	1	—	—	—	—	—	—	—	—	—	—	—	V_DD
V_SS	8	—	—	—	—	—	—	—	—	—	—	—	V_SS
OUT⁽²⁾	—	ADGRDA ADGRDB	—	CMP1	—	TMR0	CCP1 CCP2 PWM3 PWM4 PWM5	CLC1OUT CLC2OUT CLC3OUT CLC4OUT	SCL1 SCK1 SDA1 SDO1	TX1 DT1 CK1	—	—	—
Note: This is a PPS remappable input signal. The input function may be moved from the default location shown to any PORTx pin. All output signals shown in this row are PPS remappable. This is a bidirectional signal. For normal operation, user software must map this signal to the same pin via the PPS input and PPS output registers. Only available on the 8-pin PIC16F18015.

Table 3-2. 14/16-Pin Allocation Table
I/O	14-Pin PDIP SOIC TSSOP	16-Pin QFN	ADC	DAC	Comparator	ZCD	Timers	CCP	CLC	MSSP	EUSART	IOC	Interrupt	Basic
RA0	13	12	ANA0	DAC1OUT1	C1IN0+	—	—	—	—	—	—	IOCA0	—	ICSPDAT ICDDAT
RA1	12	11	ANA1 V_REF+(ADC)	DAC1REF0+	C1IN0-	—	—	—	—	—	—	IOCA1	—	ICSPCLK ICDCLK
RA2	11	10	ANA2	DAC1REF0-	—	ZCD1	T0CKI⁽¹⁾	—	—	—	—	IOCA2	INT⁽¹⁾	—
RA3	4	3	—	—	—	—	—	—	—	—	—	IOCA3	—	MCLR V_PP
RA4	3	2	ANA4	—	—	—	T1G⁽¹⁾	—	—	—	—	IOCA4	—	CLKOUT SOSCO
RA5	2	1	ANA5	—	—	—	T1CKI⁽¹⁾ T2IN⁽¹⁾	—	CLCIN3⁽¹⁾	—	—	IOCA5	—	CLKIN SOSCI
RC0	10	9	ANC0	—	—	—	—	—	—	SCL1^(1,3,4) SCK1^(1,3,4)	—	IOCC0	—	—
RC1	9	8	ANC1	—	C1IN1-	—	T4IN ⁽¹⁾	—	CLCIN2⁽¹⁾	SDA1^(1,3,4) SDI1^(1,3,4)	—	IOCC1	—	—
RC2	8	7	ANC2 ADACT⁽¹⁾	—	C1IN2-	—	T6IN ⁽¹⁾	—	—	—	—	IOCC2	—	—
RC3	7	6	ANC3	—	C1IN3-	—	—	CCP2⁽¹⁾	CLCIN0⁽¹⁾	SS1⁽¹⁾	—	IOCC3	—	—
RC4	6	5	ANC4	—	—	—	T3G⁽¹⁾	—	CLCIN1⁽¹⁾	—	CK1^(1,3)	IOCC4	—	—
RC5	5	4	ANC5	—	—	—	T3CKI⁽¹⁾	CCP1⁽¹⁾	—	—	RX1⁽¹⁾ DT1^(1,3)	IOCC5	—	—
V_DD	1	16	—	—	—	—	—	—	—	—	—	—	—	V_DD
V_SS	14	13	—	—	—	—	—	—	—	—	—	—	—	V_SS
OUT⁽²⁾	—	—	ADGRDA ADGRDB	—	CMP1	—	TMR0	CCP1 CCP2 PWM3 PWM4 PWM5	CLC1OUT CLC2OUT CLC3OUT CLC4OUT	SCL1 SCK1 SDA1 SDO1	TX1 DT1 CK1	—	—	—
Note: This is a PPS remappable input signal. The input function may be moved from the default location shown to any PORTx pin. All output signals shown in this row are PPS remappable. This is a bidirectional signal. For normal operation, user software must map this signal to the same pin via the PPS input and PPS output registers. These pins can be configured for I²C or SMBus logic levels via the RxyI2C registers. The SCL1/SDA1 signals may be assigned to these pins for expected operation. PPS assignments of these signals to other pins will operate; however, the logic levels will be standard TTL/ST as selected by the INLVL register.