6.12 Peripheral Pin Select (PPS) Input Mapping Register Summary

See the PPS module in the Product Memory Mapping Overview from Related Links for base address.

Table 6-15. Peripheral Pin Select Input Registers
OffsetNameBit PositionBits
76543210
0x000EXTINT0R7:0EXTINT0R[3:0]
15:8
23:16
31:24
0x004EXTINT1R7:0EXTINT1R[3:0]
15:8
23:16
31:24
0x008EXTINT2R7:0EXTINT2R[3:0]
15:8
23:16
31:24
0x00CEXTINT3R7:0EXTINT3R[3:0]
15:8
23:16
31:24
0x03CNMIR7:0NMIR[3:0]
15:8
23:16
31:24
0x040SCOM0P0R7:0SCOM0P0R[3:0]
15:8
23:16
31:24
0x044SCOM0P1R7:0SCOM0P1R[3:0]
15:8
23:16
31:24
0x048SCOM0P2R7:0SCOM0P2R[3:0]
15:8
23:16
31:24
0x04CSCOM0P3R7:0SCOM0P3R[3:0]
15:8
23:16
31:24
0x050SCOM1P0R7:0SCOM1P0R[3:0]
15:8
23:16
31:24
0x054SCOM1P1R7:0SCOM1P1R[3:0]
15:8
23:16
31:24
0x058SCOM1P2R7:0SCOM1P2R[3:0]
15:8
23:16
31:24
0x05CSCOM1P3R7:0SCOM1P3R[3:0]
15:8
23:16
31:24
0x084 QD0R 7:0 QD0R[3:0]
15:8
23:16
31:24
0x088 QD1R 7:0 QD1R[3:0]
15:8
23:16
31:24
0x08C QD2R 7:0 QD2R[3:0]
15:8
23:16
31:24
0x090 QD3R 7:0 QD3R[3:0]
15:8
23:16
31:24
0x094 REFIR 7:0 REFIR[3:0]
15:8
23:16
31:24
0x098 CCLIN0R 7:0 CCLIN0R[3:0]
15:8
23:16
31:24
0x09C CCLIN1R 7:0 CCLIN1R[3:0]
15:8
23:16
31:24
0x0A0 CCLIN2R 7:0 CCLIN2R[3:0]
15:8
23:16
31:24
0x0A4 CCLIN3R 7:0 CCLIN3R[3:0]
15:8
23:16
31:24
0x0A8 CCLIN4R 7:0 CCLIN4R[3:0]
15:8
23:16
31:24
0x0AC CCLIN5R 7:0 CCLIN5R[3:0]
15:8
23:16
31:24
0x0B0 TC0WO0G1R 7:0 TC0WO0G1R[3:0]
15:8
23:16
31:24
0x0B4 TC0WO0G2R 7:0 TC0WO0G2R[3:0]
15:8
23:16
31:24
0x0B8 TC0WO1G3R 7:0 TC0WO1G3R[3:0]
15:8
23:16
31:24
0x0BC TC0WO1G4R 7:0 TC0WO1G4R[3:0]
15:8
23:16
31:24
0x0C0 TC1WO0G1R 7:0 TC1WO0G1R[3:0]
15:8
23:16
31:24
0x0C4 TC1WO1G2R 7:0 TC1WO0G2R[3:0]
15:8
23:16
31:24
0x0C8 TC2WO0G1R 7:0 TC2WO0G1R[3:0]
15:8
23:16
31:24
0x0CC TC2WO0G3R 7:0 TC2WO0G3R[3:0]
15:8
23:16
31:24
0x0D0 TC2WO1G2R 7:0 TC2WO1G2R[3:0]
15:8
23:16
31:24
0x0D4 TC2WO1G4R 7:0 TC2WO1G4R[3:0]
15:8
23:16
31:24
0x0D8 TC3WO0G1R 7:0 TC3WO0G1R[3:0]
15:8
23:16
31:24
0x0DC TC3WO0G3R 7:0TC3WO0G3R[3:0]
15:8
23:16
31:24
0x0E0 TC3WO1G2R 7:0 TC3WO1G2R[3:0]
15:8
23:16
31:24
0x0E4 TC3WO1G4R 7:0 TC3WO1G4R[3:0]
15:8
23:16
31:24
0x0E8 TC4WO0G1R 7:0 TC4WO0G1R[3:0]
15:8
23:16
31:24
0x0EC TC4WO0G3R 7:0TC4WO0G3R[3:0]
15:8
23:16
31:24
0x0F0 TC4WO1G2R 7:0 TC4WO1G2R[3:0]
15:8
23:16
31:24
0x0F4 TC4WO1G4R 7:0 TC4WO1G4R[3:0]
15:8
23:16
31:24
0x0F8 TC5WO0G1R 7:0 TC5WO0G1R[3:0]
15:8
23:16
31:24
0x0FC TC5WO0G3R 7:0TC5WO0G3R[3:0]
15:8
23:16
31:24
0x100 TC5WO1G2R 7:0 TC5WO1G2R[3:0]
15:8
23:16
31:24
0x104 TC5WO1G4R 7:0 TC5WO1G4R[3:0]
15:8
23:16
31:24
0x108 TC6WO0G1R 7:0 TC6WO0G1R[3:0]
15:8
23:16
31:24
0x10C TC6WO0G3R 7:0TC6WO0G3R[3:0]
15:8
23:16
31:24
0x110 TC6WO1G2R 7:0 TC6WO1G2R[3:0]
15:8
23:16
31:24
0x114 TC6WO1G4R 7:0 TC6WO1G4R[3:0]
15:8
23:16
31:24
0x118 TC7WO0G1R 7:0 TC7WO0G1R[3:0]
15:8
23:16
31:24
0x11C TC7WO0G3R 7:0TC7WO0G3R[3:0]
15:8
23:16
31:24
0x120 TC7WO1G2R 7:0 TC7WO1G2R[3:0]
15:8
23:16
31:24
0x124 TC7WO1G4R 7:0 TC7WO1G4R[3:0]
15:8
23:16
31:24