37.7.2 CVD ADC Configuration Register
| Name: | CVDADC |
| Offset: | 0x04 |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DIGEN | DIFFPEN | SELRES[1:0] | |||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bit 3 – DIGEN
| Value | Description |
|---|---|
| 1 | Shared ADC is digital enabled |
| 0 | Shared ADC is digital disabled |
Bit 2 – DIFFPEN
| Value | Description |
|---|---|
| 1 | ANN0 (Differential) enabled |
| 0 | ANN0 (Differential) disabled |
Bits 1:0 – SELRES[1:0] Shared ADC Resolution bits
0’.Note: Changing the resolution of the ADC does not shift the result in the corresponding ADCDATAx register. The result will still occupy 12 bits, with the corresponding lower unused bits set to ‘
0’. For example, a resolution of 6 bits will result in ADCDATAx[5:0] being set to ‘0’ and ADCDATAx[11:6] holding the result.| Value | Description |
|---|---|
| 00 | 6 bits |
| 01 | 8 bits |
| 10 | 10 bits |
| 11 | 12 bits (default) |