| Document |
- Data sheet status changed to “Completed”: final
limits added to the Electrical Characteristics,
Typical Characteristics expanded, and package top
markings added
- Editorial updates throughout the document
|
| CPUINT | Description of the IVSEL bit in the CTRLA register
improved: When the entire Flash is configured as BOOT
section, the IVSEL bit in the CTRLA register is
ignored. |
| PORT | Slew rate limitation functionality added: Slew Rate Limit
Enable (SLR) bit in the Port Control (PORTCTRL)
register. |
| USART | Description of the IREI bit in the EVCTRL register
corrected |
| TWI | CTRLA.SDASETUP is used in client mode to select the clock hold
time to ensure minimum setup time |
| ADC | PGA initialization time is 20 µs |
| Electrical Characteristics |
|
| Typical Characteristics | Plots added |