31.1.4 Conversion Clock

The conversion clock source is selected with the CS bit. When CS = 1, the ADC clock source is an internal fixed-frequency clock referred to as ADCRC. When CS = 0, the ADC clock source is derived from FOSC.

Important: When CS = 0, the clock can be divided using the ADCLK register to meet the ADC clock period requirements.

The time to complete one bit conversion is defined as the TAD. Refer to Figure 31-2 for the complete timing details of the ADC conversion.

For correct conversion, the appropriate TAD specification must be met. Refer to the ADC Timing Specifications table in the “Electrical Specifications” chapter of the device data sheet for more details. The table below gives examples of appropriate ADC clock selections.

Table 31-1. ADC Clock Period (TAD) vs. Device Operating Frequencies(1,3)
ADC Clock SourceADCLKADC Clock Period (TAD) for Different Device Frequency (FOSC)
32 MHz20 MHz16 MHz8 MHz4 MHz1 MHz
FOSC/2‘b00000062.5 ns(2)100 ns(2)125 ns(2)250 ns(2)500 ns2.0 μs
FOSC/4‘b000001125 ns(2)200 ns(2)250 ns(2)500 ns1.0 μs4.0 μs
FOSC/6‘b000010187.5 ns(2)300 ns(2)375 ns(2)750 ns1.5 μs6.0 μs
FOSC/8‘b000011250 ns(2)400 ns(2)500 ns1.0 μs2.0 μs8.0 μs
........................
FOSC/16‘b000111500 ns800 ns1.0 μs2.0 μs4.0 μs16.0 μs(2)
........................
FOSC/32‘b0011111.0 μs1.6 μs2.0 μs4.0 μs8.0 μs32.0 μs(2)
........................
FOSC/64‘b01111112.0 μs3.2 μs4.0 μs8.0 μs16.0 μs(2)64.0 μs(2)
........................
FOSC/128‘b1111114.0 μs6.4 μs8.0 μs16.0 μs(2)32.0 μs(2)128.0 μs(2)
ADCRCCS = 11.0-6.0 μs1.0-6.0 μs1.0-6.0 μs1.0-6.0 μs1.0-6.0 μs1.0-6.0 μs
Note:
  1. Refer to the "Electrical Specifications" chapter of the device data sheet to see the TAD parameter for the ADCRC source typical TAD value.
  2. These values violate the required TAD time.
  3. The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the system clock FOSC. However, the ADCRC oscillator source must be used when conversions are to be performed with the device in Sleep mode.
Important:
  • Except for the ADCRC clock source, any changes in the system clock frequency will change the ADC clock frequency, which may adversely affect the ADC result.
  • The internal control logic of the ADC runs off of the clock selected by the CS bit. When the CS bit is set to ‘1’ (ADC runs on ADCRC), there may be unexpected delays in operation when setting the ADC control bits.
Figure 31-2. Analog-to-Digital Conversion Cycles