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PIC16F18054/55/74/75 Full-Featured, 28/40-Pin Microcontrollers
Introduction
PIC16F180 Family Summary
Core Features
Memory
Operating Characteristics
Power-Saving Functionality
Digital Peripherals
Analog Peripherals
Clocking Structure
Programming/Debug Features
Block Diagram
1 Packages
2 Pin Diagrams
3 Pin Allocation Tables
4 Guidelines for Getting Started with PIC16F180 Microcontrollers
4.1 Basic Connection Requirements
4.2 Power Supply Pins
4.3 Master Clear (MCLR) Pin
4.4 In-Circuit Serial Programming™ (ICSP™) Pins
4.5 Unused I/Os
5 Register and Bit Naming Conventions
5.1 Register Names
5.2 Bit Names
5.3 Register and Bit Naming Exceptions
6 Register Legend
7 Enhanced Mid-Range CPU
7.1 Automatic Interrupt Context Saving
7.2 16-Level Stack with Overflow and Underflow
7.3 File Select Registers
7.4 Instruction Set
8 Device Configuration
8.1 Configuration Words
8.2 Code Protection
8.3 Write Protection
8.4 User ID
8.5 Device ID and Revision ID
8.6 Register Definitions: Configuration Settings
8.7 Register Definitions: Device ID and Revision ID
9 Memory Organization
9.1 Program Memory Organization
9.2 Data Memory Organization
9.3 STATUS Register
9.4 PCL and PCLATH
9.5 Stack
9.6 Indirect Addressing
9.7 Register Definitions: Memory Organization
9.8 Register Summary - Memory Organization
10 Resets
10.1 Power-on Reset (POR)
10.2 Brown-out Reset (BOR)
10.3 MCLR Reset
10.4 Watchdog Timer (WDT) Reset
10.5 RESET Instruction
10.6 Stack Overflow/Underflow Reset
10.7 Power-Up Timer (PWRT)
10.8 Start-Up Sequence
10.9 Memory Execution Violation
10.10 Determining the Cause of a Reset
10.11 Power Control (PCONx) Register
10.12 Register Definitions: Power Control
10.13 Register Summary - Power Control
11 OSC - Oscillator Module
11.1 Clock Source Types
11.2 Active Clock Tuning (ACT)
11.3 Register Definitions: Oscillator Module
11.4 Register Summary - Oscillator Module
12 INT - Interrupts
12.1 Overview
12.2 INTCON Register
12.3 PIE Registers
12.4 PIR Registers
12.5 Operation
12.6 Interrupt Latency
12.7 Interrupts During Sleep
12.8 INT Pin
12.9 Automatic Context Saving
12.10 Register Definitions: Interrupt Control
12.11 Register Summary - Interrupt Control
13 Sleep Mode
13.1 Sleep Mode Operation
14 WDT - Watchdog Timer
14.1 Selectable Clock Sources
14.2 WDT Operating Modes
14.3 WDT Time-Out Period
14.4 Clearing the WDT
14.5 WDT Operation During Sleep
14.6 Register Definitions: WDT Control
14.7 Register Summary - WDT Control
15 NVM - Nonvolatile Memory Control
15.1 Program Flash Memory (PFM)
15.2 Data Flash Memory (DFM)
15.3 Register Definitions: Nonvolatile Memory Control
15.4 Register Summary - NVM Control
16 I/O Ports
16.1 Overview
16.2 PORTx - Data Register
16.3 LATx - Output Latch
16.4 TRISx - Direction Control
16.5 ANSELx - Analog Control
16.6 WPUx - Weak Pull-Up Control
16.7 INLVLx - Input Threshold Control
16.8 SLRCONx - Slew Rate Control
16.9 ODCONx - Open-Drain Control
16.10 Edge Selectable Interrupt-on-Change
16.11 I2C Pad Control
16.12 I/O Priorities
16.13 MCLR/VPP/RE3 Pin
16.14 Register Definitions: Port Control
16.15 Register Summary - IO Ports
17 IOC - Interrupt-on-Change
17.1 Overview
17.2 Enabling the Module
17.3 Individual Pin Configuration
17.4 Interrupt Flags
17.5 Clearing Interrupt Flags
17.6 Operation in Sleep
17.7 Register Definitions: Interrupt-on-Change Control
17.8 Register Summary - Interrupt-on-Change
18 PPS - Peripheral Pin Select Module
18.1 Overview
18.2 PPS Inputs
18.3 PPS Outputs
18.4 Bidirectional Pins
18.5 PPS Lock
18.6 Operation During Sleep
18.7 Effects of a Reset
18.8 Register Definitions: Peripheral Pin Select (PPS)
18.9 Register Summary - Peripheral Pin Select Module
19 TMR0 - Timer0 Module
19.1 Timer0 Operation
19.2 Clock Selection
19.3 Timer0 Output and Interrupt
19.4 Operation During Sleep
19.5 Register Definitions: Timer0 Control
19.6 Register Summary - Timer0
20 TMR1 - Timer1 Module with Gate Control
20.1 Timer1 Operation
20.2 Clock Source Selection
20.3 Timer1 Prescaler
20.4 Secondary Oscillator
20.5 Timer1 Operation in Asynchronous Counter Mode
20.6 Timer1 16-Bit Read/Write Mode
20.7 Timer1 Gate
20.8 Timer1 Interrupt
20.9 Timer1 Operation During Sleep
20.10 CCP Capture/Compare Time Base
20.11 CCP Special Event Trigger
20.12 Peripheral Module Disable
20.13 Register Definitions: Timer1 Control
20.14 Register Summary - Timer1
21 TMR2 - Timer2 Module
21.1 Timer2 Operation
21.2 Timer2 Output
21.3 External Reset Sources
21.4 Timer2 Interrupt
21.5 PSYNC Bit
21.6 CSYNC Bit
21.7 Operating Modes
21.8 Operation Examples
21.9 Timer2 Operation During Sleep
21.10 Register Definitions: Timer2 Control
21.11 Register Summary - Timer2
22 NCO - Numerically Controlled Oscillator Module
22.1 NCO Operation
22.2 Fixed Duty Cycle Mode
22.3 Pulse Frequency Mode
22.4 Output Polarity Control
22.5 Interrupts
22.6 Effects of a Reset
22.7 Operation in Sleep
22.8 Register Definitions: NCO
22.9 Register Summary - NCO
23 CWG - Complementary Waveform Generator Module
23.1 Fundamental Operation
23.2 Operating Modes
23.3 Clock Source
23.4 Selectable Input Sources
23.5 Output Control
23.6 Dead-Band Control
23.7 Rising Edge and Reverse Dead Band
23.8 Falling Edge and Forward Dead Band
23.9 Dead-Band Jitter
23.10 Auto-Shutdown
23.11 Auto-Shutdown Restart
23.12 Operation During Sleep
23.13 Configuring the CWG
23.14 Register Definitions: CWG Control
23.15 Register Summary - CWG
24 CCP - Capture/Compare/PWM Module
24.1 CCP Module Configuration
24.2 Capture Mode
24.3 Compare Mode
24.4 PWM Overview
24.5 Register Definitions: CCP Control
24.6 Register Summary - CCP Control
25 Capture, Compare, and PWM Timers Selection
25.1 Register Definitions: Capture, Compare, and PWM Timers Selection
25.2 Register Summary - Capture, Compare, and PWM Timers Selection
26 PWM - Pulse-Width Modulation
26.1 Fundamental Operation
26.2 PWM Output Polarity
26.3 PWM Period
26.4 PWM Duty Cycle
26.5 PWM Resolution
26.6 Operation in Sleep Mode
26.7 Changes in System Clock Frequency
26.8 Effects of Reset
26.9 Setup for PWM Operation Using PWMx Output Pins
26.10 Setup for PWM Operation to Other Device Peripherals
26.11 Register Definitions: PWM Control
26.12 Register Summary - PWM
27 PWM Timers Selection
27.1 Register Definitions: Capture, Compare, and PWM Timers Selection
27.2 Register Summary - Capture, Compare, and PWM Timers Selection
28 CLC - Configurable Logic Cell
28.1 CLC Setup
28.2 CLC Interrupts
28.3 Effects of a Reset
28.4 Output Mirror Copies
28.5 Operation During Sleep
28.6 CLC Setup Steps
28.7 Register Overlay
28.8 Register Definitions: Configurable Logic Cell
28.9 Register Summary - CLC Control
29 MSSP - Host Synchronous Serial Port Module
29.1 SPI Mode Overview
29.2 I2C Mode Overview
29.3 Baud Rate Generator
29.4 Register Definitions: MSSP Control
29.5 Register Summary - MSSP Control
30 EUSART - Enhanced Universal Synchronous Asynchronous Receiver Transmitter
30.1 EUSART Asynchronous Mode
30.2 Clock Accuracy with Asynchronous Operation
30.3 EUSART Baud Rate Generator (BRG)
30.4 EUSART Synchronous Mode
30.5 EUSART Operation During Sleep
30.6 Register Definitions: EUSART Control
30.7 Register Summary - EUSART
31 ADC - Analog-to-Digital Converter with Computation Module
31.1 ADC Configuration
31.2 ADC Operation
31.3 ADC Acquisition Requirements
31.4 Computation Operation
31.5 Register Definitions: ADC Control
31.6 Register Summary - ADC
32 DAC - Digital-to-Analog Converter Module
32.1 Output Voltage Selection
32.2 Ratiometric Output Level
32.3 Buffered DAC Output Range Selection
32.4 Operation During Sleep
32.5 Effects of a Reset
32.6 Register Definitions: DAC Control
32.7 Register Summary - DAC
33 CMP - Comparator Module
33.1 Comparator Overview
33.2 Comparator Control
33.3 Comparator Output Synchronization
33.4 Comparator Hysteresis
33.5 Comparator Interrupt
33.6 Comparator Positive Input Selection
33.7 Comparator Negative Input Selection
33.8 Comparator Response Time
33.9 Analog Input Connection Considerations
33.10 Operation in Sleep Mode
33.11 ADC Auto-Trigger Source
33.12 Register Definitions: Comparator Control
33.13 Register Summary - Comparator
34 FVR - Fixed Voltage Reference
34.1 Independent Gain Amplifiers
34.2 FVR Stabilization Period
34.3 Register Definitions: FVR
34.4 Register Summary - FVR
35 Temperature Indicator Module
35.1 Module Operation
35.2 Temperature Calculation
35.3 ADC Acquisition Time
35.4 Register Definitions: Temperature Indicator
35.5 Register Summary - Temperature Indicator
36 ZCD - Zero-Cross Detection Module
36.1 External Resistor Selection
36.2 ZCD Logic Output
36.3 ZCD Logic Polarity
36.4 ZCD Interrupts
36.5 Correction for ZCPINV Offset
36.6 Handling VPEAK Variations
36.7 Operation During Sleep
36.8 Effects of a Reset
36.9 Disabling the ZCD Module
36.10 Register Definitions: ZCD Control
36.11 Register Summary - ZCD
37 Charge Pump
37.1 Manually Enabled
37.2 Automatically Enabled
37.3 Disabled
37.4 Charge Pump Oscillator
37.5 Charge Pump Threshold
37.6 Charge Pump Ready
37.7 Register Definitions: Charge Pump
37.8 Register Summary - Charge Pump
38 Instruction Set Summary
38.1 Read-Modify-Write Operations
38.2 Standard Instruction Set
39 ICSP™ - In-Circuit Serial Programming™
39.1 High-Voltage Programming Entry Mode
39.2 Low-Voltage Programming Entry Mode
39.3 Common Programming Interfaces
40 Register Summary
41 Electrical Specifications
41.1 Absolute Maximum Ratings(†)
41.2 Standard Operating Conditions
41.3 DC Characteristics
41.4 AC Characteristics
42 DC and AC Characteristics Graphs and Tables
43 Packaging Information
43.1 Package Details
44 Appendix A: Revision History
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