30.4.2.4 Synchronous Client Reception Setup

  1. Set the SYNC and SPEN bits and clear the CSRC bit.
  2. Select the receive input pin by writing the appropriate value to the RXxPPS register.
  3. Select the clock input pin by writing the appropriate values to the TXxPPS register.
  4. Clear the ANSEL bit for both the TXx/CKx and RXx/DTx pins (if applicable).
  5. If interrupts are desired, set the RCxIE bit of the PIEx register and the GIE and PEIE bits of the INTCON register.
  6. If 9-bit reception is desired, set the RX9 bit.
  7. Set the CREN bit to enable reception.
  8. The RCxIF bit will be set when reception is complete. An interrupt will be generated if the RCxIE bit was set.
  9. If 9-bit mode is enabled, retrieve the Most Significant bit from the RX9D bit.
  10. Retrieve the eight Least Significant bits from the receive FIFO by reading the RCxREG register.
  11. If an overrun error occurs, clear the error by either clearing the CREN bit or by clearing the SPEN bit which resets the EUSART.