20.13.4 TxGATE

Timer Gate Source Selection Register

Name:	TxGATE
Offset:	0x0290,0x0296


Bit	7	6	5	4	3	2	1	0
				GSS[4:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0

Bits 4:0 – GSS[4:0] Timer Gate Source Selection

Table 20-5. Timer Gate Sources
GSS	Gate Source
GSS	Timer1	Timer3
`11111-10011`	Reserved
`10010`	CLC4_OUT
`10001`	CLC3_OUT
`10000`	CLC2_OUT
`01111`	CLC1_OUT
`01110`	ZCD_OUT
`01101`	C1_OUT
`01100`	NCO1_OUT
`01011`	PWM5_OUT
`01010`	PWM4_OUT
`01001`	PWM3_OUT
`01000`	CCP2_OUT
`00111`	CCP1_OUT
`00110`	TMR6_Postscaled_OUT
`00101`	TMR4_Postscaled_OUT
`00100`	TMR3_overflow	Reserved
`00011`	TMR2_Postscaled_OUT
`00010`	Reserved	TMR1_overflow
`00001`	TMR0_overflow
`00000`	Pin selected by T1GPPS	Pin selected by T3GPPS

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.