29.3 Baud Rate Generator

The MSSP module has a Baud Rate Generator (BRG) available for clock generation in both I2C and SPI Host modes. The BRG reload value is placed in the SSPxADD register. When a write occurs to SSPxBUF, the BRG will automatically begin counting down. MSSP Baud Rate Generator Frequency Equation shows how the value for SSPxADD is calculated.

Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state.

An internal Reload signal, shown in Figure 29-41, triggers the value from SSPxADD to be loaded into the BRG counter. This occurs twice for each oscillation of the module clock line.

Table 29-2 illustrates clock rates based on instruction cycles and the BRG value loaded into SSPxADD.

MSSP Baud Rate Generator Frequency Equation

FCLOCK=FOSC4×(SSPxADD+1)
Figure 29-41. Baud Rate Generator Block Diagram
Important: Values of 0x00, 0x01 and 0x02 are not valid for SSPxADD when used as a Baud Rate Generator for I2C. This is an implementation limitation.
Table 29-2. MSSP Clock Rate w/BRG
FOSCFCYBRG ValueFCLOCK 
(2 Rollovers of BRG)
32 MHz8 MHz13h400 kHz
32 MHz8 MHz19h308 kHz
32 MHz8 MHz4Fh100 kHz
16 MHz4 MHz09h400 kHz
16 MHz4 MHz0Ch308 kHz
16 MHz4 MHz27h100 kHz
4 MHz1 MHz09h100 kHz
Note: Refer to the I/O port electrical specifications in the “Electrical Specifications” chapter, Internal Oscillator Parameters, to ensure the system is designed to support all requirements.