2.1 General

The CLASSD can be used either as a digital-to-analog converter (DAC) or as a digital power amplifier.

• To use the CLASSD as a DAC, set the CLASSD_MR.NON_OVERLAP bit to 0. The CLASSD then outputs either one signal per channel (Single-Ended mode) or two signals per channel (Differential mode). As a DAC, it is expected to be buffered with a low-pass (LP) filter.
• To use the CLASSD as a digital power amplifier, set CLASSD_MR.NON_OVERLAP to 1. The CLASSD then outputs either two signals per channel (Single-Ended mode) to drive a pair of complementary power MOS devices (half bridge), or four signals per channel (Differential mode) to drive two complementary pairs of power MOS devices (full bridge).

  The low-impedance load is driven by the external power transistors, which can be connected to a higher voltage supply to significantly increase the output power. In Single-Ended mode, a blocking capacitor is generally required to suppress the DC component in the output signal, and an LC filter is used to attenuate the strong carrier frequency component of the output signal. In Differential mode, the load must not be referenced to ground but instead driven from both ends. No blocking capacitor is needed, and an LC filter may or may not be used, depending on the required EMC level and signal quality.

In all cases, the output signals are PWM signals with a base frequency of 768 kHz when the source stream is sampled at 8, 16, 32, 48 or 96 kHz, or 705.6 kHz when the source stream is sampled at 22.05, 44.1 or 88.2 kHz.

The device data sheets provide some common examples. This application note describes how to simulate these examples using MPLAB® Mindi™ and describes several variants of these circuits, along with computation and simulation details to guide users toward a working solution for their application.