4.1 Synchronization

The Anchor nodes within a TDoA system require a synchronized clock to determine the timestamp differences. This can be achieved with the help of wired or wireless synchronization.

In wired synchronization, a common system clock is distributed to all Anchor nodes, which includes the system clock and the synchronization signal. This is achieved by omitting one clock pulse in the distributed clock signal at regular intervals. The following figure shows such a 48 MHz clock signal with an omitted clock pulse occurring at every 10 ms.

Figure 4-1. External 48 MHz Clock Signal with Synchronization Pulse

In wireless synchronization, each Anchor node has its own 48 MHz clock source. The synchronization is performed with internally-generated sync pulses occurring every 170 µs and requires a calibration at regular intervals with a reference Tag device.

The UWB demo kit, as shown in Figure 3-1, supports only wireless synchronization. A specialized UWB TDoA demo kit with two ATA5352-EB2 modules and clock/synchronization logic supports the generation of the wired synchronization signal, as shown in Figure 3-4.

The following figure shows the hardware implementation of the UWB TDoA demo kit necessary to generate the combined clock/synchronization signal for the two ATA8352 UWB transceiver modules mounted on the demo kit PCB.

Figure 4-2. UWB TDoA External Clock/Synchronization Signal

The Sync_Ena signal is high pulse generated within the software application of the host MCU with a typical duration of ~10 µs, and it is generated in regular intervals of about 10 ms. The synchronization pulse hardware generates the combined Clock/Sync signal on the ATA53UWB-XPRO baseboard, which is distributed to the two UWB ATA5352-EB2 modules with the ATA8352 UWB device. A resistor divider on the module adapts the 3.3V Clock/Sync signal to the 1.25V core domain voltage.

The captured timestamp information from the payload data during TX and RX operation is built with the two counter bb_t_cnt and sync_cnt, as described in the ATA8352 Impulse-Radio Ultra-Wideband (IR-UWB) Transceiver User's Guide (DS50003125) in section 5.6 and equation 5-19 with a resolution of ~165 ps. It might be sufficient in cases of short Sync_Ena pulse intervals to use only the bb_t_cnt value, but ensure that all modules have recognized the latest sync pulse. This can be checked by reading the actual sync counter value from register A20 ID = 111 before and after the sync signal.