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PIC16F17526/46 Full-Featured 14/20-Pin Microcontrollers
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PIC16F17526
PIC16F17546
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51
Appendix A: Revision History
Introduction
PIC16F17576
Family Summary
Core Features
1
Packages
2
Pin Diagrams
3
Pin Allocation Tables
4
Guidelines for Getting Started with
PIC16F17576
Microcontrollers
5
Register and Bit Naming Conventions
6
Register Legend
7
Enhanced Mid-Range CPU
8
Device Configuration
9
Memory Organization
10
Resets
11
OSC - Oscillator Module (With Fail-Safe Clock Monitor)
12
INT - Interrupts
13
Power-Saving Modes
14
WWDT - Windowed Watchdog Timer
15
NVM - Nonvolatile Memory Control
16
I/O Ports
17
SRPORT – Signal Routing Port
18
IOC - Interrupt-on-Change
19
PPS - Peripheral Pin Select Module
20
CRC - Cyclic Redundancy Check Module with Memory Scanner
21
PMD - Peripheral Module Disable
22
CLKREF - Reference Clock Output Module
23
TMR0 - Timer0 Module
24
TMR1 - Timer1 Module with Gate Control
25
TMR2 - Timer2 Module
26
NCO - Numerically Controlled Oscillator Module
27
CCP - Capture/Compare/PWM Module
28
Capture, Compare, and PWM Timers Selection
29
PWM - Pulse-Width Modulator with Compare
30
CWG - Complementary Waveform Generator Module
31
CLC - Configurable Logic Cell
32
MSSP - Host Synchronous Serial Port Module
33
EUSART - Enhanced Universal Synchronous Asynchronous Receiver Transmitter
34
APM - Analog Peripheral Manager
35
ADC - Analog-to-Digital Converter with Computation Module
36
OPA - Operational Amplifier
37
DAC - Digital-to-Analog Converter Module
38
CMP - Comparator Module
39
CMPLP - Low-Power Comparator Module
40
VREFLP – Low-Power Voltage Reference Module
41
FVR - Fixed Voltage Reference
42
Temperature Indicator Module
43
ZCD - Zero-Cross Detection Module
44
Charge Pump
45
Instruction Set Summary
46
ICSP™ - In-Circuit Serial Programming™
47
Register Summary
48
Electrical Specifications
49
DC and AC Characteristics Graphs and Tables
50
Packaging Information
51
Appendix A: Revision History
52
Product Identification System
Microchip Information
51 Appendix A: Revision History
Doc. Rev.
Date
Comments
A
06/2025
Initial document release.
