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PIC16F17526/46 Full-Featured 14/20-Pin Microcontrollers
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PIC16F17526
PIC16F17546
Introduction
PIC16F17576
Family Summary
Core Features
Memory
Operating Characteristics
Power-Saving Functionality
Digital Peripherals
Analog Peripherals
Clocking Structure
Programming/Debug Features
Block Diagram
1
Packages
2
Pin Diagrams
3
Pin Allocation Tables
4
Guidelines for Getting Started with
PIC16F17576
Microcontrollers
4.1
Basic Connection Requirements
4.2
Power Supply Pins
4.3
Master Clear (
MCLR
) Pin
4.4
In-Circuit Serial Programming™ (ICSP™) Pins
4.5
Unused I/Os
5
Register and Bit Naming Conventions
5.1
Register Names
5.2
Bit Names
5.3
Register and Bit Naming Exceptions
6
Register Legend
7
Enhanced Mid-Range CPU
7.1
Automatic Interrupt Context Saving
7.2
16
-Level Stack with Overflow and Underflow
7.3
File Select Registers
7.4
Instruction Set
8
Device Configuration
8.1
Configuration Words
8.2
Code Protection
8.3
Write Protection
8.4
User ID
8.5
Device ID and Revision ID
8.6
Register Definitions: Configuration Settings
8.7
Register Definitions: Device ID and Revision ID
9
Memory Organization
9.1
Program Memory Organization
9.2
Data Memory Organization
9.3
STATUS Register
9.4
PCL and PCLATH
9.5
Stack
9.6
Indirect Addressing
9.7
Register Definitions: Memory Organization
9.8
Register Summary - Memory Organization
10
Resets
10.1
Power-on Reset (POR)
10.2
Brown-out Reset (BOR)
10.3
MCLR
Reset
10.4
Windowed Watchdog Timer (WWDT) Reset
10.5
Watchdog Timer (WDT) Reset
10.6
RESET
Instruction
10.7
Stack Overflow/Underflow Reset
10.8
Power-Up Timer (PWRT)
10.9
Start-Up Sequence
10.10
Memory Execution Violation
10.11
Determining the Cause of a Reset
10.12
Power Control (PCONx) Register
10.13
Register Definitions: Power Control
10.14
Register Summary - Power Control
11
OSC - Oscillator Module (With Fail-Safe Clock Monitor)
11.1
Clock Source Types
11.2
Clock Switching
11.3
Fail-Safe Clock Monitor (FSCM)
11.4
Active Clock Tuning (ACT)
11.5
Register Definitions: Oscillator Module
11.6
Register Summary - Oscillator Module
12
INT - Interrupts
12.1
Overview
12.2
INTCON Register
12.3
PIE Registers
12.4
PIR Registers
12.5
Operation
12.6
Interrupt Latency
12.7
Interrupts During Sleep
12.8
INT Pin
12.9
Automatic Context Saving
12.10
Register Definitions: Interrupt Control
12.11
Register Summary - Interrupt Control
13
Power-Saving Modes
13.1
Doze Mode
13.2
Sleep Mode
13.3
Idle Mode
13.4
Peripheral Operation in Power-Saving Modes
13.5
Register Definitions: Power-Savings Control
13.6
Register Summary - Power-Savings Control
14
WWDT - Windowed Watchdog Timer
14.1
Independent Clock Source
14.2
WWDT Operating Modes
14.3
Time-Out Period
14.4
Watchdog Window
14.5
Clearing the Watchdog Timer
14.6
Operation During Sleep
14.7
Register Definitions: Windowed Watchdog Timer Control
14.8
Register Summary - WDT Control
15
NVM - Nonvolatile Memory Control
15.1
Program Flash Memory (PFM)
15.2
Data Flash Memory (DFM)
15.3
Register Definitions: Nonvolatile Memory Control
15.4
Register Summary - NVM Control
16
I/O Ports
16.1
Overview
16.2
PORTx - Data Register
16.3
LATx - Output Latch
16.4
TRISx - Direction Control
16.5
ANSELx - Analog Control
16.6
WPUx - Weak Pull-Up Control
16.7
INLVLx - Input Threshold Control
16.8
SLRCONx - Slew Rate Control
16.9
ODCONx - Open-Drain Control
16.10
Edge Selectable Interrupt-on-Change
16.11
I
2
C Pad Control
16.12
I/O Priorities
16.13
MCLR
/V
PP
/RA3
Pin
16.14
Register Definitions: Port Control
16.15
Register Summary - I/O Ports
17
SRPORT – Signal Routing Port
17.1
Operation
17.2
Software Setup
17.3
Register Definitions: Signal Routing Port
17.4
Register Summary - Signal Routing Port
18
IOC - Interrupt-on-Change
18.1
Overview
18.2
Enabling the Module
18.3
Individual Pin Configuration
18.4
Interrupt Flags
18.5
Clearing Interrupt Flags
18.6
Operation in Sleep
18.7
Register Definitions: Interrupt-on-Change Control
18.8
Register Summary - Interrupt-on-Change
19
PPS - Peripheral Pin Select Module
19.1
Overview
19.2
PPS Inputs
19.3
PPS Outputs
19.4
Bidirectional Pins
19.5
PPS Lock
19.6
Operation During Sleep
19.7
Effects of a Reset
19.8
Register Definitions: Peripheral Pin Select (PPS)
19.9
Register Summary - Peripheral Pin Select Module
20
CRC - Cyclic Redundancy Check Module with Memory Scanner
20.1
Module Overview
20.2
Polynomial Implementation
20.3
Data Sources
20.4
CRC Check Value
20.5
CRC Interrupt
20.6
Configuring the CRC Module
20.7
Scanner Module Overview
20.8
Scanning Modes
20.9
Configuring the Scanner
20.10
Scanner Interrupts
20.11
WWDT Interaction
20.12
Operation During Sleep
20.13
Peripheral Module Disable
20.14
Register Definitions: CRC and Scanner Control
20.15
Register Summary - CRC
21
PMD - Peripheral Module Disable
21.1
Overview
21.2
Disabling a Module
21.3
Enabling a Module
21.4
Register Definitions: Peripheral Module Disable
21.5
Register Summary - PMD
22
CLKREF - Reference Clock Output Module
22.1
Clock Source
22.2
Programmable Clock Divider
22.3
Selectable Duty Cycle
22.4
Operation in Sleep Mode
22.5
Register Definitions: Reference Clock
22.6
Register Summary - Reference CLK
23
TMR0 - Timer0 Module
23.1
Timer0 Operation
23.2
Clock Selection
23.3
Timer0 Output and Interrupt
23.4
Operation During Sleep
23.5
Register Definitions: Timer0 Control
23.6
Register Summary - Timer0
24
TMR1 - Timer1 Module with Gate Control
24.1
Timer1 Operation
24.2
Clock Source Selection
24.3
Timer1 Prescaler
24.4
Secondary Oscillator
24.5
Timer1 Operation in Asynchronous Counter Mode
24.6
Timer1 16-Bit Read/Write Mode
24.7
Timer1 Gate
24.8
Timer1 Interrupt
24.9
Timer1 Operation During Sleep
24.10
CCP Capture/Compare Time Base
24.11
CCP Special Event Trigger
24.12
Peripheral Module Disable
24.13
Register Definitions: Timer1 Control
24.14
Register Summary - Timer1
25
TMR2 - Timer2 Module
25.1
Timer2 Operation
25.2
Timer2 Output
25.3
External Reset Sources
25.4
Timer2 Interrupt
25.5
PSYNC Bit
25.6
CSYNC Bit
25.7
Operating Modes
25.8
Operation Examples
25.9
Timer2 Operation During Sleep
25.10
Register Definitions: Timer2 Control
25.11
Register Summary - Timer2
26
NCO - Numerically Controlled Oscillator Module
26.1
NCO Operation
26.2
Fixed Duty Cycle Mode
26.3
Pulse Frequency Mode
26.4
Output Polarity Control
26.5
Interrupts
26.6
Effects of a Reset
26.7
Operation in Sleep
26.8
Register Definitions: NCO
26.9
Register Summary - NCO
27
CCP - Capture/Compare/PWM Module
27.1
CCP Module Configuration
27.2
Capture Mode
27.3
Compare Mode
27.4
PWM Overview
27.5
Register Definitions: CCP Control
27.6
Register Summary - CCP Control
28
Capture, Compare, and PWM Timers Selection
28.1
Register Definitions: Capture, Compare, and PWM Timers Selection
28.2
Register Summary - Capture, Compare, and PWM Timers Selection
29
PWM - Pulse-Width Modulator with Compare
29.1
Output Slices
29.2
Period Timer
29.3
Clock Sources
29.4
External Period Resets
29.5
Buffered Period and Parameter Registers
29.6
Synchronizing Multiple PWMs
29.7
Interrupts
29.8
Operation During Sleep
29.9
Register Definitions: PWM Control
29.10
Register Summary - PWM
30
CWG - Complementary Waveform Generator Module
30.1
Fundamental Operation
30.2
Operating Modes
30.3
Clock Source
30.4
Selectable Input Sources
30.5
Output Control
30.6
Dead-Band Control
30.7
Rising Edge and Reverse Dead Band
30.8
Falling Edge and Forward Dead Band
30.9
Dead-Band Jitter
30.10
Auto-Shutdown
30.11
Auto-Shutdown Restart
30.12
Operation During Sleep
30.13
Configuring the CWG
30.14
Register Definitions: CWG Control
30.15
Register Summary - CWG
31
CLC - Configurable Logic Cell
31.1
CLC Setup
31.2
CLC Interrupts
31.3
Effects of a Reset
31.4
Output Mirror Copies
31.5
Operation During Sleep
31.6
CLC Setup Steps
31.7
Register Overlay
31.8
Register Definitions: Configurable Logic Cell
31.9
Register Summary - CLC Control
32
MSSP - Host Synchronous Serial Port Module
32.1
SPI Mode Overview
32.2
I
2
C Mode Overview
32.3
Baud Rate Generator
32.4
Register Definitions: MSSP Control
32.5
Register Summary - MSSP Control
33
EUSART - Enhanced Universal Synchronous Asynchronous Receiver Transmitter
33.1
EUSART Asynchronous Mode
33.2
Clock Accuracy with Asynchronous Operation
33.3
EUSART Baud Rate Generator (BRG)
33.4
EUSART Synchronous Mode
33.5
EUSART Operation During Sleep
33.6
Register Definitions: EUSART Control
33.7
Register Summary - EUSART
34
APM - Analog Peripheral Manager
34.1
Analog Peripheral Manager Control
34.2
Analog Peripheral Manager Operation
34.3
Analog Peripheral Manager Setup
34.4
Register Definitions: Analog Peripheral Manager
34.5
Register Summary - Analog Peripheral Manager
35
ADC - Analog-to-Digital Converter with Computation Module
35.1
ADC Configuration
35.2
ADC Operation
35.3
Starting a Conversion
35.4
ADC Acquisition Requirements
35.5
Computation Operation
35.6
Register Definitions: ADC Control
35.7
Register Summary - ADC
36
OPA - Operational Amplifier
36.1
OPA Module Control
36.2
Input Offset Voltage
36.3
OPA Operation with ADC
36.4
Register Definitions: Operational Amplifier
36.5
Register Summary - Operational Amplifier
37
DAC - Digital-to-Analog Converter Module
37.1
Output Voltage Selection
37.2
Ratiometric Output Level
37.3
Buffered DAC Output Range Selection
37.4
Operation During Sleep
37.5
Effects of a Reset
37.6
Register Definitions: DAC Control
37.7
Register Summary - DAC
38
CMP - Comparator Module
38.1
Comparator Overview
38.2
Comparator Control
38.3
Comparator Hysteresis
38.4
Comparator Interrupt
38.5
Comparator Positive Input Selection
38.6
Comparator Negative Input Selection
38.7
Comparator Response Time
38.8
Analog Input Connection Considerations
38.9
Operation in Sleep Mode
38.10
ADC Auto-Trigger Source
38.11
Register Definitions: Comparator Control
38.12
Register Summary - Comparator
39
CMPLP - Low-Power Comparator Module
39.1
Low-Power Comparator Overview
39.2
Comparator Control
39.3
Low-Power Comparator Input Common-Mode Voltage Range Selection
39.4
Comparator Interrupt
39.5
Comparator Positive Input Selection
39.6
Comparator Negative Input Selection
39.7
Comparator Response Time
39.8
Analog Input Connection Considerations
39.9
Operation in Sleep Mode
39.10
ADC Auto-Trigger Source
39.11
Register Definitions: Comparator Control
39.12
Register Summary - Low-Power Comparator
40
VREFLP – Low-Power Voltage Reference Module
40.1
Low-Power Voltage Reference
40.2
Low-Power DAC Reference
40.3
Ready Status
40.4
Register Definitions: Low-Power Voltage Reference
40.5
Register Summary - Low-Power Voltage Reference
41
FVR - Fixed Voltage Reference
41.1
Independent Gain Amplifiers
41.2
FVR Stabilization Period
41.3
Register Definitions: FVR
41.4
Register Summary - FVR
42
Temperature Indicator Module
42.1
Module Operation
42.2
Temperature Calculation
42.3
ADC Acquisition Time
42.4
Register Definitions: Temperature Indicator
42.5
Register Summary - Temperature Indicator
43
ZCD - Zero-Cross Detection Module
43.1
External Resistor Selection
43.2
ZCD Logic Output
43.3
ZCD Logic Polarity
43.4
ZCD Interrupts
43.5
Correction for Z
CPINV
Offset
43.6
Handling V
PEAK
Variations
43.7
Operation During Sleep
43.8
Effects of a Reset
43.9
Disabling the ZCD Module
43.10
Register Definitions: ZCD Control
43.11
Register Summary - ZCD
44
Charge Pump
44.1
Manually Enabled
44.2
Automatically Enabled
44.3
Disabled
44.4
Charge Pump Oscillator
44.5
Charge Pump Threshold
44.6
Charge Pump Ready
44.7
Register Definitions: Charge Pump
44.8
Register Summary - Charge Pump
45
Instruction Set Summary
45.1
Read-Modify-Write Operations
45.2
Standard Instruction Set
46
ICSP™ - In-Circuit Serial Programming™
46.1
High-Voltage Programming Entry Mode
46.2
Low-Voltage Programming Entry Mode
46.3
Common Programming Interfaces
47
Register Summary
48
Electrical Specifications
48.1
Absolute Maximum Ratings
48.2
Standard Operating Conditions
48.3
DC Characteristics
48.4
AC Characteristics
49
DC and AC Characteristics Graphs and Tables
50
Packaging Information
50.1
Package Details
51
Appendix A: Revision History
52
Product Identification System
Microchip Information
Trademarks
Legal Notice
Microchip Devices Code Protection Feature
