24.3.3.2 Output

Timer synchronization and output logic level depend on the selected Timer Mode (CNTMODE) bit field in the Control B (TCBn.CTRLB) register. In Single-Shot mode, the timer/counter can be configured so that the signal generation happens asynchronously to an incoming event (ASYNC = 1 in TCBn.CTRLB). Then, the output signal is set immediately at the incoming event instead of being synchronized to the TCB clock. Due to synchronization delay for the counter, the waveform output will be set high three to four CLK_TCB cycles more than what is defined by the TOP value.

Writing the Compare/Capture Output Enable (CCMPEN) bit in TCBn.CTRLB to ‘1’ enables the waveform output, making the waveform output available on the corresponding pin, overriding the value in the corresponding PORT output register.

The table below lists the different configurations and their impact on the output.

Table 24-2. Output Configuration
CCMPEN	CNTMODE	ASYNC	Output
`1`	Single-Shot mode	`0`	The output is high when the counter starts and low when the counter stops
	Single-Shot mode	`1`	The output is high when the event arrives and low when the counter stops
	8-bit PWM mode	Not applicable	8-bit PWM mode
	Other modes	Not applicable	The Compare/Capture Pin Initial Value (CCMPINIT) bit in the Control B (TCBn.CTRLB) register selects the initial output level
`0`	Not applicable	Not applicable	No output

Changing modes while the peripheral is enabled is not recommended, as this can produce an unpredictable output. There is a possibility that an interrupt flag is set during the timer configuration. It is recommended to clear the Timer/Counter Interrupt Flags (TCBn.INTFLAGS) register after configuring the peripheral.