Figure 40-157. Open Loop Gain
and Phase Bodeplot
Figure 40-158. Phase Margin
Over Temperature and VDD
Figure 40-159. Phase Margin Over VDD and Temperature
Figure 40-160. Gain Bandwidth Product Over Temperature and
VDD
Figure 40-161. Gain Bandwidth Product Over VDD and
Temperature
Figure 40-162. PSRR Over
Frequency and Temperature
Figure 40-163. Voltage Noise
Density for GND with IRSEL = 1
and CPU Mode =
Standby
Figure 40-164. Voltage Noise
Density for OP2 with IRSEL = 1
and CPU Mode =
Standby
Figure 40-165. Slew Rate
Falling Over VDD and Temperature
Figure 40-166. Slew Rate
Rising Over VDD and Temperature
Figure 40-167. Output
Impedance Over Frequency
Figure 40-168. Small-Signal
Non-Inverting Pulse Response
Figure 40-169. Large-Signal
Non-Inverting Pulse Response
Figure 40-170. Offset Over
VCM with VDD = 1.8V
Figure 40-171. Offset Over
VCM with VDD = 3.0V
Figure 40-172. Offset at 25°C
Over VCM with VDD = 5.5V
Figure 40-173. Offset Over
VCM with VDD = 1.8V and IRSEL =
1
Figure 40-174. Offset Over
VCM with VDD = 3.0V and IRSEL =
1
Figure 40-175. Offset Over
VCM with VDD = 5.5V and IRSEL =
1
Figure 40-176. Offset Over
VCM and Temperature
Figure 40-177. Offset Over
VCM and Temperature with IRSEL =
1
Figure 40-178. Offset Over
Temperature with VDD = 1.8V
Figure 40-179. Offset Over
Temperature with VDD = 3.0V
Figure 40-180. Offset Over
Temperature with VDD = 5.5V
Figure 40-181. PSRR at DC
Over VDD and Temperature
Figure 40-182. CMRR at DC
Over VDD and Temperature
Figure 40-183. Open Loop Gain
Over VDD and Temperature
Figure 40-184. Open Loop Gain
Over Temperature and VDD
Figure 40-185. Output Sinking
Short Circuit Current Over VDD and
Temperature
Figure 40-186. Output
Sourcing Short Circuit Current Over VDD and
Temperature
Figure 40-187. VOH
Over Temperature and Load Current
Figure 40-188. VOL
Over Temperature and Load Current
Figure 40-189. IDD
= Standby Over VDD and Temperature With IRSEL =
All