38.4.4 I/O Pins

Table 38-7.  I/O Pin Specifications (1) (5)
Symbol Description Min. Typ.✝ Max. Units Conditions
Input Low Voltage
VIL I/O PORT:
  • With Schmitt Trigger buffer
 — — 0.2 × VDD V PINnCTRL.INLVL = 0x00
  • TTL level
 — — 0.8 V

PINnCTRL.INLVL = 0x01

VDD > 2.7V
TWI PORT:
  • With I2C levels
 — — 0.3 × VDD V CTRLA.INPUTLVL = 0x0
  • With SMBus 3.0 levels
 0.8 V CTRLA.INPUTLVL = 0x1
RESET Pin — — 0.2 × VDD V
Input High Voltage
VIH I/O PORT:
  • With Schmitt Trigger buffer
 0.8 × VDD — — V PINnCTRL.INLVL = 0x00
  • TTL level
 2.0 — — V

PINnCTRL.INLVL = 0x01

VDD > 2.7V
TWI PORT:
  • With I2C levels
 0.7 × VDD — — V CTRLA.INPUTLVL = 0x0
  • With SMBus 3.0 levels
 1.35 — — V CTRLA.INPUTLVL = 0x1

0°C ≤ TA ≤ +125°C,

2.5V ≤ VDD ≤ 5.5V
1.45 — — V CTRLA.INPUTLVL = 0x1

0°C ≤ TA ≤ +125°C,

1.8V ≤ VDD ≤ 5.5V
RESET Pin 0.8 × VDD — — V
Input Leakage Current(2)
IIL I/O PORTS(3) — ±5 ±125 nA GND ≤ VPIN ≤ VDD,

pin at high-impedance, TA= 85°C
— ±5 ±1000 nA GND ≤ VPIN ≤ VDD,

pin at high-impedance, TA = 125°C
RESET Pin(4) * — ±50 ±200 nA GND ≤ VPIN ≤ VDD,

pin at high-impedance, TA= 85°C
Pull-up Current
IPUR 90 150 200 μA VDD = 3.0V, VPIN = GND
Output Low Voltage
VOL Standard I/O Ports — — 0.6 V IOL = 10 mA, VDD = 3.0V
Output High Voltage
VOH Standard I/O Ports VDD - 0.7 — — V IOH = 6 mA, VDD = 3.0V
I/O Slew Rate
Rising slew rate — 22 — ns PORTCTRL.SRL = 0x00
Rising slew rate — 45 — ns PORTCTRL.SRL = 0x01
Falling slew rate — 30 — ns PORTCTRL.SRL = 0x01
Falling slew rate — 16 — ns PORTCTRL.SRL = 0x00
Pin Capacitance
CIO VREFpin — 7 — pF
XTAL pins — 4 — pF
Other pins — 4 — pF

✝ Data in the “Typ.” column is at TA = 25°C and VDD = 3.0V unless otherwise specified. These parameters are for design guidance only and are not tested.

* These parameters are characterized but not tested in production.

Note:
  1. These figures are valid for all I/O ports regardless of if they are connected to the VDD or VDDIO2 power domain.
  2. The negative current is the current sourced by the pin.
  3. The leakage current numbers for I/O PORTS are also valid when the pin is used as input to an enabled analog peripheral.
  4. The leakage current on the RESET pin strongly depends on the applied voltage level. The specified levels represent normal operating conditions. A higher leakage current may be measured at different input voltages.
  5. The input voltage threshold is relative to VDDIO2 on MVIO pins (PORTC) and VDD on other pins.