38.4.1 Supply Voltage

Table 38-4. Supply Voltage
SymbolMin.Typ. ✝Max.UnitsConditions
Supply Voltage(1)
VDD

1.8

—

5.5

V

VDDIO2

1.62

—

5.5

V

Slew Rate——1.5V/µs1.8V ≤ VDD ≤ 5.5V
RAM Data Retention(2)
VDR

1.7

—

—

V

Device in Power-Down mode
Power-on Reset Release Voltage(4)
VPOR

—

1.6

—

V

BOD disabled(3)
tPOR

—

1

—

μs

BOD disabled(3)
Power-on Reset Re-Arm Voltage(4)
VPORR

—

1.25

—

V

BOD disabled(3)
tPORR

—

2.7

—

μs

BOD disabled(3)
VDD Rise Rate to Ensure Internal Power-on Reset Signal(4)
SVDD0.05

—

—

V/msBOD disabled(3)

✝ Data in the “Typ.” column is at TA = 25°C and VDD = 3.0V unless otherwise specified. These parameters are not tested and are for design guidance only.

Note:
  1. During Chip Erase, the Brown-out Detector (BOD) configured with BODLEVEL0 is forced ON. The erase attempt will fail if the supply voltage VDD is below VBOD for BODLEVEL0.
  2. This is the limit to which VDD can be lowered in sleep mode without losing RAM data.
  3. Refer to RST and BOD section for BOD trip point information.
  4. Refer to Figure 38-1.
Figure 38-1. POR and PORR with Slow Rising VDD
Note:
  • When POR is low, the device is held in Reset