33.5.4 Control D


Bit	7	6	5	4	3	2	1	0
	INITDLY[2:0]				SAMPDLY[3:0]
Access	R/W	R/W	R/W		R/W	R/W	R/W	R/W
Reset	0	0	0		0	0	0	0

Bits 7:5 – INITDLY[2:0] Initialization Delay

This bit field defines the initialization delay before the first sample when enabling the ADC or changing to an internal reference voltage. Setting this delay will ensure that the components of the ADC are ready before starting the first conversion. The initialization delay will also be applied when waking up from a deep sleep to do a measurement.

The delay is expressed as a number of CLK_ADC cycles.

Value	Name	Description
0x0	DLY0	Delay 0 CLK_ADC cycles
0x1	DLY16	Delay 16 CLK_ADC cycles
0x2	DLY32	Delay 32 CLK_ADC cycles
0x3	DLY64	Delay 64 CLK_ADC cycles
0x4	DLY128	Delay 128 CLK_ADC cycles
0x5	DLY256	Delay 256 CLK_ADC cycles
Other	-	Reserved

Bits 3:0 – SAMPDLY[3:0] Sampling Delay

This bit field defines the delay between consecutive ADC samples. This allows modifying the sampling frequency used during hardware accumulation, to suppress periodic noise that may otherwise disturb the sampling. The delay is expressed as CLK_ADC cycles and is given directly by the bit field setting.

Value	Name	Description
0x0	DLY0	Delay 0 CLK_ADC cycles
0x1	DLY1	Delay 1 CLK_ADC cycles
0x2	DLY2	Delay 2 CLK_ADC cycles
...	...
0xF	DLY15	Delay 15 CLK_ADC cycles

Name:	CTRLD
Offset:	0x03
Reset:	0x00
Property:	-