33.5.3 Control C

Name:	CTRLC
Offset:	0x02
Reset:	0x00
Property:	-


Bit	7	6	5	4	3	2	1	0
					PRESC[3:0]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0

Bits 3:0 – PRESC[3:0] Prescaler

This bit field defines the division factor from the peripheral clock (CLK_PER) to the ADC clock (CLK_ADC).

Value	Name	Description
0x0	DIV2	CLK_PER divided by 2
0x1	DIV4	CLK_PER divided by 4
0x2	DIV8	CLK_PER divided by 8
0x3	DIV12	CLK_PER divided by 12
0x4	DIV16	CLK_PER divided by 16
0x5	DIV20	CLK_PER divided by 20
0x6	DIV24	CLK_PER divided by 24
0x7	DIV28	CLK_PER divided by 28
0x8	DIV32	CLK_PER divided by 32
0x9	DIV48	CLK_PER divided by 48
0xA	DIV64	CLK_PER divided by 64
0xB	DIV96	CLK_PER divided by 96
0xC	DIV128	CLK_PER divided by 128
0xD	DIV256	CLK_PER divided by 256
Other	-	Reserved

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