5.3.8 14-byte Config Bits Registers with Extended Instruction Set

This is the generated header file for the Configuration bits driver.

//CONFIG1L
#pragma config RETEN = ON    // VREG Sleep Enable bit->Enabled
#pragma config INTOSCSEL = HIGH    // LF-INTOSC Low-power Enable bit->LF-INTOSC in High-power mode during Sleep
#pragma config SOSCSEL = HIGH    // SOSC Power Selection and mode Configuration bits->High Power SOSC circuit selected
#pragma config XINST = OFF    // Extended Instruction Set->Disabled

//CONFIG1H
#pragma config FOSC = INTIO2    // Oscillator Selection bits->Internal RC oscillator
#pragma config FCMEN = OFF    // Fail-Safe Clock Monitor Enable bit->Disabled
#pragma config IESO = OFF    // Internal/External Oscillator Switchover bit->Disabled
#pragma config PLLCFG = OFF    // 4X PLL Enable->Disabled

//CONFIG2L
#pragma config PWRTEN = OFF    // Power-up Timer Enable bit->Disabled
#pragma config BOREN = SBORDIS    // Brown-out Reset Enable bits->Enabled in hardware, SBOREN disabled
#pragma config BORV = 3    // Brown Out Reset Voltage bits->1.8V
#pragma config BORPWR = ZPBORMV    // BORMV Power level->ZPBORMV instead of BORMV is selected

//CONFIG2H
#pragma config WDTEN = OFF    // Watchdog Timer Enable bits->WDT disabled in hardware; SWDTEN bit disabled
#pragma config WDTPS = 1048576    // Watchdog Timer Postscale Select bits->1:1048576

//CONFIG3L
#pragma config RTCOSC = SOSCREF    // RTCC Clock Select->RTCC uses SOSC
#pragma config EASHFT = ON    // External Address Shift bit->Address Shifting enabled
#pragma config ABW = MM    // Address Bus Width Select bits->8-bit address bus
#pragma config BW = 16    // Data Bus Width->16-bit external bus mode
#pragma config WAIT = OFF    // External Bus Wait->Disabled

//CONFIG3H
#pragma config MCLRE = ON    // MCLR Pin Enable bit->MCLR Enabled, RG5 Disabled
#pragma config CCP2MX = PORTC    // CCP2 MUX bit->RC1
#pragma config MSSPMSK = MSK7    // MSSP address masking->7 Bit address masking mode
#pragma config ECCPMX = PORTE    // ECCP Mux->Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RE6/RE5/RE4/RE3

//CONFIG4L
#pragma config STVREN = ON    // Stack Full/Underflow Reset Enable bit->Enabled
#pragma config BBSIZ = BB2K    // Boot Block Size Select bit->2K word Boot Block size
#pragma config DEBUG = OFF    // Background Debug->Disabled

//CONFIG5L
#pragma config CP0 = OFF    // Code Protection Block 0->Disabled
#pragma config CP1 = OFF    // Code Protection Block 1->Disabled
#pragma config CP2 = OFF    // Code Protection Block 2->Disabled
#pragma config CP3 = OFF    // Code Protection Block 3->Disabled
#pragma config CP4 = OFF    // Code Protect 10000-13FFF->Disabled
#pragma config CP5 = OFF    // Code Protect 14000-17FFF->Disabled
#pragma config CP6 = OFF    // Code Protect 18000-1BFFF->Disabled
#pragma config CP7 = OFF    // Code Protect 1C000-1FFFF->Disabled

//CONFIG5H
#pragma config CPB = OFF    // Boot Block Code Protection bit->Disabled
#pragma config CPD = OFF    // Data EEPROM Code Protection bit->Disabled

//CONFIG6L
#pragma config WRT0 = OFF    // Write Protection Block 0->Disabled
#pragma config WRT1 = OFF    // Write Protection Block 1->Disabled
#pragma config WRT2 = OFF    // Write Protection Block 2->Disabled
#pragma config WRT3 = OFF    // Write Protection Block 3->Disabled
#pragma config WRT4 = OFF    // Table Write Protect 10000-13FFF->Disabled
#pragma config WRT5 = OFF    // Table Write Protect 14000-17FFF->Disabled
#pragma config WRT6 = OFF    // Table Write Protect 18000-1BFFF->Disabled
#pragma config WRT7 = OFF    // Table Write Protect 1C000-1FFFF->Disabled

//CONFIG6H
#pragma config WRTC = OFF    // Configuration Register Write Protection bit->Disabled
#pragma config WRTB = OFF    // Boot Block Write Protection bit->Disabled
#pragma config WRTD = OFF    // Data EEPROM Write Protection bit->Disabled

//CONFIG7L
#pragma config EBTR0 = OFF    // Table Read Protection Block 0->Disabled
#pragma config EBTR1 = OFF    // Table Read Protection Block 1->Disabled
#pragma config EBTR2 = OFF    // Table Read Protection Block 2->Disabled
#pragma config EBTR3 = OFF    // Table Read Protection Block 3->Disabled
#pragma config EBRT0 = OFF    // Table Read Protect 00800-03FFF->Disabled
#pragma config EBRT1 = OFF    // Table Read Protect 04000-07FFF->Disabled
#pragma config EBRT2 = OFF    // Table Read Protect 08000-0BFFF->Disabled
#pragma config EBRT3 = OFF    // Table Read Protect 0C000-0FFFF->Disabled
#pragma config EBRT4 = OFF    // Table Read Protect 10000-13FFF->Disabled
#pragma config EBRT5 = OFF    // Table Read Protect 14000-17FFF->Disabled
#pragma config EBRT6 = OFF    // Table Read Protect 18000-1BFFF->Disabled
#pragma config EBRT7 = OFF    // Table Read Protect 1C000-1FFFF->Disabled

//CONFIG7H
#pragma config EBTRB = OFF    // Boot Block Table Read Protection bit->OFF
#pragma config EBRTB = OFF    // Table Read Protect Boot->Disabled

This is the generated header file for the System driver.

This is the generated Device Configuration bits file.

CONFIGURATION BITS Generated Driver Source File

CONFIGURATION BITS Generated Driver Header File

• void SYSTEM_Initialize (void)

  Initializes the system module. This routine is called only once during system initialization, before calling other APIs.

This file contains the API implementation for the System driver.

System Driver Source File

• void SYSTEM_Initialize (void)

  Initializes the system module. This routine is called only once during system initialization, before calling other APIs.

System Driver Header File