3.1.6 External Clock

A clarification has been made to Table 9-16 Start-Up Times for the External Clock Selection, where 14 CK in the column Additional Delay from Reset (VCC = 5.0V) has been replaced by 19 CK. Functional changes are shown in bold.

Table 9-16. Start-Up Times for the External Clock Selection

Power ConditionsStart-Up Time from Power-Down and Power-SaveAdditional Delay from Reset (VCC = 5.0V)SUT[1:0]
BOD enabled6 CK19 CK(1)00
Fast rising power6 CK19 CK + 4.1 ms01
Slow rising power6 CK19 CK + 65 ms(2)10
Reserved11
Note:
  1. If the RSTDISBL fuse is programmed, this start-up time will be increased to 
19 CK + 4 ms to ensure the programming mode can be entered.
  2. The device is shipped with this option selected.