1.26.7 ARM MMU v5

ARM926EJ-S MMU is an ARM architecture v5 MMU. It provides virtual memory features required by systems operating on platforms such as Symbian OS, WindowsCE, and Linux. A single set of two-level page tables stored in main memory is used to control the address translation, permission checks, and memory region attributes for both data and instruction accesses. The MMU uses a single unified Translation Look aside Buffer (TLB) to cache the information held in the page tables. To support both sections and pages, there are two levels of address translation. The MMU puts the translated physical addresses into the MMU Translation Look aside Buffer TLB.

The MMU TLB has two parts: the main TLB and lock down TLB.

The main TLB is a two-way, set-associative cache for page table information. It has 32 entries per way for a total of 64 entries. The lock down TLB is an eight-entry fully-associative cache that contains locked TLB entries. Locking TLB entries can ensure that a memory access to a given region never incurs the penalty of a page table walk.

Using The Library

MMU Plib Initializes MMU with a flat address map (e.g. physical and virtual addresses are the same) and enable MMU and caches by invoking MMU_Initialize() in the system initialization.

Library Interface

ARM MMU v5 peripheral library provides the following interfaces:

Functions

Name	Description
MMU_Initialize	Initialize and enable MMU
icache_InvalidateAll	Invalidate instruction cache
icache_Enable	Enable instruction cache
icache_Disable	Disable instruction cache
dcache_InvalidateAll	Invalidate Data Cache
dcache_CleanAll	Clean Data Cache
dcache_CleanInvalidateAll	Clean and Invalidate Data Cache
dcache_InvalidateByAddr	Invalidate Data Cache by address
dcache_CleanByAddr	Clean Data Cache by address
dcache_CleanInvalidateByAddr	Clean Data Cache by address
dcache_Enable	Enable L1 data cache
dcache_Disable	Disable L1 data cache