3.4 Instruction Stalls

In order to maximize device throughput, all instructions are pipelined. A consequence of this pipelining is that address register data dependencies may arise between successive read and write operations using common registers.

‘Read-After-Write’ (RAW) dependencies occur across instruction boundaries and are detected by the hardware. An example of a RAW dependency would be a write operation that modifies W5, followed by a read operation that uses W5 as an Address Pointer. The contents of W5 will not be valid for the read operation until the earlier write completes. This problem is resolved by stalling the instruction execution for one instruction cycle, which allows the write to complete before the next read is started.