3.4.1 RAW Dependency Detection
During the Read-After-Write (RAW) instruction predecode, the core determines if any address register dependency is imminent across an instruction boundary. The stall detection logic compares the W register (if any) used for the destination EA of the instruction currently being executed with the W register to be used by the source EA (if any) of the prefetched instruction. When a match between the destination and source registers is identified, a set of rules is applied to decide whether or not to stall the instruction by one cycle. Table 3-6 lists various RAW conditions that cause an instruction execution stall.
| Destination Addressing Mode Using Wn | Source
Addressing Mode Using Wn | Stall Required? | Examples(2)(Wn = W2) |
|---|---|---|---|
| Direct | Direct | No Stall | ADD.W W0, W1, W2
|
| Indirect | Direct | No Stall | ADD.W W0, W1, [W2]
|
| Indirect | Indirect | No Stall | ADD.W W0, W1, [W2]
|
| Indirect | Indirect with Pre/Post-Modification | No Stall | ADD.W W0, W1, [W2]
|
| Indirect with Pre/Post-Modification | Direct | No Stall | ADD.W W0, W1, [W2++]
|
| Direct | Indirect | Stall(1) | ADD.W W0, W1, W2
|
| Direct | Indirect with Pre/Post-Modification | Stall(1) | ADD.W W0, W1, W2
|
| Indirect | Indirect | Stall(1) | ADD.W W0, W1, [W2](2)
|
| Indirect | Indirect with Pre/Post-Modification | Stall(1) | ADD.W W0, W1, [W2](2)
|
| Indirect with Pre/Post-Modification | Indirect | Stall(1) | ADD.W W0, W1, [W2++]
|
| Indirect with Pre/Post-Modification | Indirect with Pre/Post-Modification | Stall(1) | ADD.W W0, W1, [W2++]
|
| When stalls are detected, one cycle is added to the instruction execution time. For these examples, the contents of W2 = the mapped address of W2 (0x0004). | |||
Ws is the same register as Wd, the old value of Ws is used for Wd (i.e., the address offset is ignored).