18.2.10 Initialize Bus Matrix Registers
On some of the PIC32 MCUs, the bus matrix registers (BMXDKPBA
,
BMXDUDBA
, BMXDUPBA
) must be initialized by the
start-up code if any RAM functions exist. The startup code leaves these registers in
their state when RAM functions do not exist in the projects. The linker collects all RAM
functions and allocates them to a section of data memory that is aligned on a
2K-alignment boundary. To determine whether any RAM functions exist in the application,
the linker provides a variable that contains the beginning address of this section. This
variable is named _ramfunc_begin
.
In addition, the linker provides a 2K-aligned variable required for the boundary register
(BMXDKPBA). The variable is named _bmxdkpba_address.
The linker also
provides two variables that contains the addresses for the bus matrix register. These
variables are named _bmxdkpba_address
,
_bmxdudba_address
, and _bmxdupba_address
.
The linker ensures that RAM functions are aligned to a 2K-alignment boundary as is required by the BMXDKPBA register.
On other PIC32 devices, no special bus initialization is required to execute RAM functions.
Initialize CP0 Registers
The CP0
registers are initialized in the following order:
Count
registerCompare
registerEBase
registerIntCtl
registerCause
registerStatus
register
Hardware Enable Register (HWREna
– CP0 Register 7, Select 0)
This register contains a bit mask that determines which hardware registers are accessible
via the RDHWR
instruction. Privileged software may determine which of
the hardware registers are accessible by the RDHWR
instruction. In
doing so, a register may be virtualized at the cost of handling a Reserved Instruction
Exception, interpreting the instruction, and returning the virtualized value. For
example, if it is not desirable to provide direct access to the Count
register, access to the register may be individually dis-abled, and the return value can
be virtualized by the operating system.
No initialization is performed on this register in the PIC32 start-up code.
Bad Virtual Address Register (BadVAddr
– CP0 Register 8, Select
0)
This register is a read-only register that captures the most recent virtual address that
caused an Address Error exception (AdEL
or AdES
).No
initialization is performed on this register in the PIC32 start-up code.
Count Register (Count
– CP0 Register 9, Select 0)
This register acts as a timer, incrementing at a constant rate, whether or not an
instruction is executed, retired, or any forward progress is made through the pipeline.
The counter increments every other clock if the DC
bit in the
Cause
register is '0
'. The Count
register can be written for functional or diagnostic purposes, including at Reset or to
synchronize processors. By writing the Count
DM
bit in
the Debug
register, it is possible to control whether the
Count
register continues incrementing while the processor is in
Debug mode. This register is cleared in the default PIC32 start-up code.
Status Register (Status
– CP0 Register 12, Select 0)
This register is a read/write register that contains the operating mode, Interrupt Enabling, and the diagnostic states of the processor. Fields of this register combine to create operating modes for the processor.
The following settings are initialized by the default PIC32 start-up code
(0b000000000x0xx0?00000000000000000
):
- Access to Coprocessor 0 not allowed in User mode (
CU0 = 0
) - User mode uses configured endianess (
RE = 0
) - No change to exception vectors location (
BEV = no change
) - No change to flag bits that indicate reason for entry to the Reset exception vector
(
SR, NMI = no change
) - Interrupt masks are cleared to disable any pending interrupt requests
(
IM7..IM2 = 0, IM1..IM0 = 0
) - Interrupt priority level is 0 (
IPL = 0
) - Base mode is Kernel mode (
UM = 0
) - Error level is normal (
ERL = 0
) - Exception level is normal (
EXL = 0
) - Interrupts are disabled (
IE = 0
)
The DSPr2 engine is enabled on target devices featuring the DSPr2 engine (MX = 1).
The IEEE 754 compliant Floating-Point Unit is enabled for target devices that support the
FPU. The FPU is configured in the FR64 mode, which defines 32 64-bit float-ing-point
general registers (FPRs) with all formats supported in each register
(CU1=1
) and (FR=1
).
Interrupt Control Register (IntCtl
– CP0 Register 12, Select
1)
This register controls the expanded interrupt capability added in Release 2 of the Architecture, including vectored interrupts and support for an external interrupt controller.
This register contains the vector spacing for interrupt handling. The vector spacing
portion of this register (bits 9..5) is initialized with the value of the
_vector_spacing
symbol by the PIC32 start-up code. All other bits
are set to '1
'.
Shadow Register Control Register (SRSCtl
– CP0 Register 12, Select
2)
This register controls the operation of the GPR shadow sets in the processor. The default startup code uses the SRSCtl register when it initializes the Global Pointer register in all register sets. However, it restores the original SRSCtl value after the GP register is initialized.
Shadow Register Map Register (SRSMap
– CP0 Register 12, Select
3)
This register contains eight 4-bit fields that provide the mapping from a vector number
to the shadow set number to use when servicing such an interrupt. The values from this
register are not used for a non-interrupt exception, or a non-vectored interrupt
(Cause
IV
= 0
or
IntCtl
VS
= 0
). In such cases, the
shadow set number comes from SRSCtlESS
. If SRSCtlHSS
is zero, the results of a software read or write of this register are UNPREDICTABLE. The
operation of the processor is UNDEFINED if a value is written to any field in this
register that is greater than the value of SRSCtlHSS
. The
SRSMap
register contains the shadow register set numbers for vector
numbers 7..0. The same shadow set number can be established for multiple interrupt
vectors, creating a many-to-one mapping from a vector to a single shadow register set
number.
No initialization is performed on this register in the PIC32 start-up code.
Cause Register (Cause
– CP0 Register 13, Select 0)
This register primarily describes the cause of the most recent exception. In addition,
fields also control software interrupt requests and the vector through which interrupts
are dispatched. With the exception of the DC
, IV
, and
IP1..IP0
fields, all fields in the Cause
register
are read-only. Release 2 of the Architecture added optional support for an External
Interrupt Controller (EIC) interrupt mode, in which IP7..IP2
are
interpreted as the Requested Interrupt Priority Level (RIPL
).
The following settings are initialized by the PIC32 start-up code:
- Enable counting of
Count
register (DC = no change
) - Use the special exception vector (
16#200
) (IV = 1
) - Disable software interrupt requests (
IP1..IP0 = 0
)
Exception Program Counter (EPC
– CP0 Register 14, Select 0)
This register is a read/write register that contains the address at which processing
resumes after an exception has been serviced. All bits of the EPC
register are significant and must be writable. For synchronous (precise) exceptions, the
EPC
contains one of the following:
- The virtual address of the instruction that was the direct cause of the exception
- The virtual address of the immediately preceding branch or jump instruction, when
the exception causing instruction is a branch delay slot and the
Branch Delay
bit in theCause
register is set.
On new exceptions, the processor does not write to the EPC
register when
the EXL
bit in the Status
register is set; however,
the register can still be written via the MTC0
instruction.
No initialization is performed on this register in the PIC32 start-up code.
Processor Identification Register (PRId
– CP0 Register 15, Select
0)
This register is a 32-bit read-only register that contains information identifying the manufacturer, manufacturer options, processor identification, and revision level of the processor.
No initialization is performed on this register in the PIC32 start-up code.
Exception Base Register (EBase
– CP0 Register 15, Select 1)
This register is a read/write register containing the base address of the exception
vectors used when Status
BEV
equals 0, and a read-only
CPU number value that may be used by software to distinguish different processors in a
multi-processor system. The EBase
register provides the ability for
software to identify the specific processor within a multi-processor system, and allows
the exception vectors for each processor to be different, especially in systems composed
of heterogeneous processors. Bits 31..12 of the EBase
register are
concatenated with zeros to form the base of the exception vectors when
Status
BEV
is 0. The exception vector base address
comes from fixed defaults when Status
BEV
is 1, or for
any EJTAG Debug exception. The Reset state of bits 31..12 of the EBase
register initialize the exception base register to 16#8000-0000
,
providing backward compatibility with Release 1 implementations. Bits 31..30 of the
EBase
register are fixed with the value 2#10
to
force the exception base address to be in KSEG0 or KSEG1 unmapped virtual address
segments.
If the value of the exception base register is to be changed, this must be done with
Status
BEV
equal 1. The operation of the processor
is UNDEFINED if the Exception Base field is written with a different value when
Status
BEV
is 0.
Combining bits 31..30 with the Exception Base field allows the base address of the exception vectors to be placed at any 4K byte page boundary. If vectored interrupts are used, a vector offset greater than 4K byte can be generated. In this case, bit 12 of the Exception Base field must be zero. The operation of the processor is UNDEFINED if software writes bit 12 of the Exception Base field with a 1 and enables the use of a vectored interrupt whose offset is greater than 4K bytes from the exception base address.
This register is initialized with the value of the _ebase_address
symbol
by the PIC32 start-up code. _ebase_address
is provided by the linker
script with a default value of the start of KSEG1 program memory. The user can change
this value by providing the command line option -–defsym
_ebase_address=A
to the linker.
Config Register (Config
– CP0 Register 16, Select 0)
This register specifies various configuration and capabilities information. Most of the
fields in the Config
register are initialized by hardware during the
Reset exception pr-ocess, or are constant.
No initialization is performed on this register in the PIC32 start-up code.
Config1 Register (Config1
– CP0 Register 16, Select 1)
This register is an adjunct to the Config
register and encodes
additional information about the capabilities present on the core. All fields in the
Config1
register are read-only.
No initialization is performed on this register in the PIC32 start-up code.
Config2 Register (Config2
– CP0 Register 16, Select 2)
This register is an adjunct to the Config
register and is reserved to
encode additional capabilities information. Config2
is allocated for
showing the configuration of level 2/3 caches. These fields are reset to 0 because L2/L3
caches are not supported on the core. All fields in the Config2
register are read-only.
No initialization is performed on this register in the PIC32 start-up code.
Config3 Register (Config3
– CP0 Register 16, Select 3)
This register encodes additional capabilities. All fields in the Config3
register are read-only.
No initialization is performed on this register in the PIC32 start-up code.
Debug Register (Debug
– CP0 Register 23, Select 0)
This register is used to control the debug exception and provide information about the
cause of the debug exception, and when re-entering at the debug exception vector due to
a normal exception in Debug mode. The read-only information bits are updated every time
the debug exception is taken, or when a normal exception is taken when already in Debug
mode. Only the DM
bit and the
EJTAG
ver
field are valid when read from non-Debug
mode. The values of all other bits and fields are UNPREDICTABLE. Operation of the
processor is UNDEFINED if the Debug
register is written from non-Debug
mode.
No initialization is performed on this register in the PIC32 start-up code.
Trace Control Register (TraceControl
– CP0 Register 23, Select
1)
This register provides control and status information. The TraceControl
register is only implemented if the EJTAG Trace capability is present.
No initialization is performed on this register in the PIC32 start-up code.
Trace Control 2 Register (TraceControl2
– CP0 Register 23, Select
2)
This register provides additional control and status information. The
TraceControl2
register is only implemented if the EJTAG Trace
capability is present.
No initialization is performed on this register in the PIC32 start-up code.
User Trace Data Register (UserTraceData
– CP0 Register 23, Select
3)
When this register is written to, a trace record is written indicating a type 1 or type 2
user format. This type is based on the UT
bit in the
TraceControl
register. This register cannot be written in
consecutive cycles. The trace output data is UNPREDICTABLE if this register is written
in consecutive cycles. The UserTraceData
register is only implemented
if the EJTAG Trace capability is present.
No initialization is performed on this register in the PIC32 start-up code.
TraceBPC Register (TraceBPC
– CP0 Register 23, Select 4)
This register is used to control start and stop of tracing using an EJTAG hardware
breakpoint. The hardware breakpoint would then be set as a triggered source and
optionally also as a Debug exception breakpoint. The TraceBPC
register
is only impl-emented if both the hardware breakpoints and the EJTAG Trace cap are
present.
No initialization is performed on this register in the PIC32 start-up code.
Debug2 Register (Debug2
– CP0 Register 23, Select 5)
This register holds additional information about complex breakpoint exceptions. The
Debug2
register is only implemented if complex hardware breakpoints
are present.
No initialization is performed on this register in the PIC32 start-up code.
Debug Exception Program Counter (DEPC
– CP0 Register 24, Select
0)
This register is a read/write register that contains the address at which processing
resumes after a debug exception or Debug mode exception has been serviced. For
synchronous (precise) debug and Debug mode exceptions, the DEPC
contains either:
- The virtual address of the instruction that was the direct cause of the debug exception, or
- The virtual address of the immediately preceding branch or jump instruction, when
the debug exception causing instruction is in a branch delay slot, and the Debug
Branch Delay (
DBD
) bit in theDebug
register is set.
For asynchronous debug exceptions (debug interrupt, complex break), the
DEPC
contains the virtual address of the instruction where
execution should resume after the debug handler code is executed.
No initialization is performed on this register in the PIC32 start-up code.
Error Exception Program Counter (ErrorEPC
– CP0 Register 30, Select
0)
This register is a read/write register, similar to the EPC
register,
except that it is used on error exceptions. All bits of the ErrorEPC
are significant and must be writable. It is also used to store the program counter on
Reset, Soft Reset, and Non-Maskable Interrupt (NMI) exceptions. The
ErrorEPC
register contains the virtual address at which
instr-uction processing can resume after servicing an error. This address can be:
- The virtual address of the instruction that caused the exception, or
- The virtual address of the immediately preceding branch or jump instruction when the error causing instruction is a branch delay slot.
Unlike the EPC
register, there is no corresponding branch delay slot
indication for the ErrorEPC
register.
No initialization is performed on this register in the PIC32 start-up code.
Debug Exception Save Register (DeSave
– CP0 Register 31, Select
0)
This register is a read/write register that functions as a simple memory location. This register is used by the debug exception handler to save one of the GPRs that is then used to save the rest of the context to a pre-determined memory area (such as in the EJTAG Probe). This register allows the safe debugging of exception handlers and other types of code where the existence of a valid stack for context saving cannot be assumed.
No initialization is performed on this register in the PIC32 start-up code.