18.2.11 Initialize CP0 Registers
The MIPS System Control Coprocessor 0 (CP0) controls interrupts and exceptions. This
coprocessor implements many registers, which are initialized by the runtime startup code
to reasonable values. Some registers (for example the PRISS
register)
should be explicitly reassigned by user code to ensure that they are correct for the
application.
The registers in the coprocessor control the DSPr2 engine and Floating-Point Unit (FPU) where these are implemented on the device. These are both enabled as part of the coprocessor initialization.