2.3 Timer

In this application, the Timer2 module is configured with a prescaler of 1:8 and a source of F_OSC/4, meaning that when the period value is set to zero, a new value will be loaded every 32 clock cycles or eight instruction cycles. This action requires a hole in the form of a branch or GOTO at least once every eight words. Since the timer value will only be updated when a hole occurs, there is an increased risk that an update will be missed if no hole occurs before another transfer is triggered. Depending on the importance of uninterrupted execution of the main application versus the importance of waveform output quality, the System Arbiter can be used to adjust the priorities to give the DMA being used as the DAC feeder a higher priority than the main execution. Another option would be to cut the frequency in half and either limit the maximum frequency of the output or cut the number of sample points in half.