27.3.2.2.3.1 Case M1: Address
Packet Transmit Complete - Direction Bit Set to ‘0’
If a slave device responds to the address
packet with an ACK, the Write Interrupt Flag (WIF) is set to ‘1’, the
Received Acknowledge (RXACK) flag is set to ‘0’, and the Clock Hold
(CLKHOLD) flag is set to ‘1’. The WIF, RXACK and CLKHOLD flags are located
in the Master Status (TWIn.MSTATUS) register.
The clock hold is active at this point, forcing the SCL low. This will stretch the low period of the clock to slow down the overall clock frequency, forcing delays required to process the data and preventing further activity on the bus.
The software can prepare to:
- Transmit data packets to the slave