4.3 Transceiver Circuit Description
The AT86RF212B single-chip radio transceiver provides a complete radio transceiver interface between radio frequency signals and baseband microcontroller. It comprises a bidirectional analog RF front end, direct-conversion mixers, low-noise fractional-n PLL, quadrature digitizer, DSP modem and baseband packet-handler optimized for IEEE 802.15.4 MAC/PHY automation and low-power. An SPI accessible 128-byte TRX buffer stores receive or transmit data. Radio communication between transmitter and receiver is based on DSSS Spread Spectrum with OQPSK or BPSK modulation schemes as defined by the IEEE 802.15.4 standard. Additional proprietary modulation modes include high-data rate payload encoding and wideband BPSK-40-ALT.
The number of required external components is minimal. The basic requirements are an antenna, a balun, harmonic filter, local oscillator and bypass capacitors. The RF Ports are bidirectional 100Ω differential signals that do not require external TX/RX switches. Hardware control signals are automatically generated for TX/RX arbitration of high-powered PA/LNA frontends and transmitter diversity for systems with dual antennas.
The AT86RF212B supports the IEEE 802.15.4‑2006 [2] standard mandatory BPSK modulation and optional O-QPSK modulation in the 868.3MHz and 915MHz bands. In addition, it supports the O-QPSK modulation defined in IEEE 802.15.4‑2011 [4] for the Chinese 780MHz band. For applications not targeting IEEE compliant networks, the radio transceiver supports proprietary High Data Rate Modes based on O-QPSK. Additionally the AT86RF212B provides BPSK-40-ALT wideband BPSK mode for compliance with FCC rule 15.247 and backward compatibility with legacy BPSK networks.
The AT86RF212B features hardware supported 128-bit security operation. The standalone AES encryption/decryption engine can be accessed in parallel to all PHY operational modes. Configuration of the AT86RF212B, reading and writing of data memory, as well as the AES hardware engine are controlled by the SPI interface and additional control signals.
On-chip low-dropout linear regulators provide clean 1.8 VDC power for critical analog and digital sub-systems. To conserve power, these rails are automatically sequenced by the transceiver’s state machine. This feature greatly improves EMC in the RF domain and reduces external power supply complexity to the simple addition of frequency compensation capacitors on the AVDD and DVDD pins.
Additional features of the Extended Feature Set are provided to simplify the interaction between radio transceiver and microcontroller.