51.3 Block Diagram

Table 51-1. Timer Counter Clock Assignment
NameDefinition
TIMER_CLOCK1GCLK [17], GLCK[45]
TIMER_CLOCK2MCK/8
TIMER_CLOCK3MCK/32
TIMER_CLOCK4MCK/128
TIMER_CLOCK5 (1) MD_SLCK
Note:
  1. The GCLK [TC_ID] frequency must be at least three times lower than peripheral clock frequency.
Figure 51-1. TC Block Diagram
Note:
  1. The above figure provides pin names of a first instance of a Timer Counter module (i.e., instance TC0). For any subsequent instances, the signal numbering increments. For example, “TCLK3- TCLK5”, "TIOA3-TIOA5” and "TIOB3-TIOB5” are the external I/O pins of a second Timer Counter module (i.e., instance TC1).
  2. QDEC connections are detailed in Figure 51-17.
Table 51-2. Channel Signal Description
Signal NameDescription
XC0, XC1, XC2Channel clock source that can be connected to TIOAx, TIOBx, TCLKx
TIMER_CLOCK1-5Channel clock source from system clocks
TIOAx

Capture mode: Timer Counter input


Waveform mode: Timer Counter output

TIOBx

Capture mode: Timer Counter input


Waveform mode: Timer Counter input/output

INTInterrupt signal output (internal signal)
SYNCSynchronization input signal (from Configuration register)