27.5.1 Slow Clock Controller Configuration Register

This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode register (SYSC_WPMR).
Name: SCKC_CR
Offset: 0x0
Reset: 0x00000001
Property: Read/Write

Bit 3130292827262524 
        TD_OSCSEL 
Access R/W 
Reset 0 
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
      OSC32BYPOSC32EN  
Access R/WR/W 
Reset 00 

Bit 24 – TD_OSCSEL Timing Domain Slow Clock Selector

ValueDescription
0 (RC) Slow clock of the timing domain is driven by the embedded 32 kHz (typical) RC oscillator.
1 (XTAL) Slow clock of the timing domain is driven by the 32.768 kHz crystal oscillator.

Bit 2 – OSC32BYP 32.768 kHz Crystal Oscillator Bypass

ValueDescription
0 32.768 kHz crystal oscillator is not bypassed.
1 32.768 kHz crystal oscillator is bypassed and accepts an external slow clock on XIN32.

Bit 1 – OSC32EN 32.768 kHz Crystal Oscillator

ValueDescription
0 32.768 kHz crystal oscillator is disabled.
1 32.768 kHz crystal oscillator is enabled.