56.6.10 TRNG Write Protection Status Register
| Name: | TRNG_WPSR |
| Offset: | 0xE8 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| ECLASS | SWETYP[3:0] | ||||||||
| Access | R | R | R | R | R | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| WPVSRC[15:8] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| WPVSRC[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SWE | SEQE | CGD | WPVS | ||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 31 – ECLASS Software Error Class (cleared on read)
| Value | Name | Description |
|---|---|---|
| 0 | WARNING | An abnormal access that does not affect system functionality. |
| 1 | ERROR |
Reading TRNG_ODATA when TRNG is disabled or used for private key bus transfer does not provide a random value. Writing to the PKB_CTRL register while a private key bus transfer is ongoing does not launch a new private key bus transfer. |
Bits 27:24 – SWETYP[3:0] Software Error Type (cleared on read)
| Value | Name | Description |
|---|---|---|
| 0 | READ_WO | TRNG is enabled and a write-only register has been read (Warning). |
| 1 | WRITE_RO | TRNG is enabled and a write access has been performed on a read-only register (Warning). |
| 2 | UNDEF_RW | Access to an undefined address. |
| 3 | TRNG_DIS |
The TRNG_ODATA register has been read when TRNG is disabled or used for private key bus transfer (Error). |
| 4 | PKB_BUSY | A write access to the PKB_CTRL register has been attempted during a private key bus transfer (Error). |
| 5 | LOCK_ERR | A write access to TRNG_WPMR has been attempted when one of the write protection bits is already locked, its corresponding lock control bit is set and the corresponding write protection bit is cleared, which looks like an unlock tentative (Warning). |
Bits 23:8 – WPVSRC[15:0] Write Protection Violation Source (cleared on read)
When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.
When WPVS=0 and SWE=1, WPVSRC reports the address of the incorrect software access. As soon as WPVS=1, WPVSRC returns the address of the write-protected violation.
Bit 3 – SWE Software Control Error (cleared on read)
| Value | Description |
|---|---|
| 0 | No software error has occurred since the last read of TRNG_WPSR. |
| 1 | A software error has occurred since the last read of TRNG_WPSR. The field SWETYP details the type of software error; the associated incorrect software access is reported in the field WPVSRC (if WPVS=0). |
Bit 2 – SEQE Internal Sequencer Error (cleared on read)
| Value | Description |
|---|---|
| 0 | No peripheral internal sequencer error has occurred since the last read of TRNG_WPSR. |
| 1 | A peripheral internal sequencer error has occurred since the last read of TRNG_WPSR. This flag is set under abnormal operating conditions. |
Bit 1 – CGD Clock Glitch Detected (cleared on read)
| Value | Description |
|---|---|
| 0 | No clock glitch has occurred since the last read of TRNG_WPSR. Under normal operating conditions, this bit is always cleared. |
| 1 | A clock glitch has occurred since the last read of TRNG_WPSR. This flag is set in case of abnormal clock signal waveform (glitch). |
Bit 0 – WPVS Write Protection Violation Status (cleared on read)
| Value | Description |
|---|---|
| 0 | No write protection violation has occurred since the last read of TRNG_WPSR. |
| 1 | A write protection violation has occurred since the last read of TRNG_WPSR. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. |