12.1.3 Chip Setup

When the chip is powered on, the processor clock (CPU_CLK) and the main system bus clock (MCK) source is the Main clock (MAINCK).

The ROM code performs a low-level initialization that follows the steps described below:

  1. PLLA initialized at a frequency of 396 MHz.
  2. Main system bus clock selection: when the PLLA is stabilized, the main system bus clock source is switched from the main clock to the PLLA clock. The PMC Status register is polled to wait for MCK Ready. Now, the CPU_CLK frequency is the same as the PLLA clock, whereas the MCK frequency is the quarter of the PLLA clock.

For clock frequencies, see Table 12-4.

Note: No external crystal or clock is needed during the external boot memories sequence. An external clock source is checked before the launch of the SAM-BA Monitor to get a more accurate clock signal for USB.